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Replace NULL checks for the set and clear registers with BUILD_ASSERTs in the iCE40 device instantiation.

@benediktibk benediktibk force-pushed the change/ice40_build_time_checks branch from 4b885de to c82b41c Compare November 19, 2024 14:23
@benediktibk benediktibk marked this pull request as ready for review November 19, 2024 14:23
@zephyrbot zephyrbot added the area: FPGA Field-Programmable Gate Array (FPGA) label Nov 19, 2024
@benediktibk benediktibk requested a review from josuah November 20, 2024 11:52
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I read the asserts as: "Either it has SPI, either it has all of creset-gpios, cdone-gpios, clk-gpios, pico-gpios, gpios-set-reg, gpios-clear-reg set".
Nice!

Replace NULL checks for the set and clear registers with BUILD_ASSERTs
in the iCE40 device instantiation.

Signed-off-by: Benedikt Schmidt <benedikt.schmidt@embedded-solutions.at>
@benediktibk benediktibk force-pushed the change/ice40_build_time_checks branch from c82b41c to b848f13 Compare November 20, 2024 14:14
@henrikbrixandersen henrikbrixandersen merged commit 53ae195 into zephyrproject-rtos:main Nov 21, 2024
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@benediktibk benediktibk deleted the change/ice40_build_time_checks branch November 22, 2024 19:23
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5 participants