Skip to content

stm32h7rs xspi Node with domain clock for peripheral clock configuration #88051

New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

Sign up for GitHub

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Merged
merged 8 commits into from
May 21, 2025
Merged

stm32h7rs xspi Node with domain clock for peripheral clock configuration #88051

Show file tree
Hide file tree
Changes from all commits
Commits
Show all changes
8 commits
Select commit Hold shift + click to select a range
0cfdd54
soc: st: stm32 Kconfig to retrieve the external Flash Base address
FRASTM May 5, 2025
c41a0c7
drivers: flash: stm32 xspi driver supports clock domain config
FRASTM May 27, 2024
c7b54c2
drivers: flash: stm32 xspi drivers supporting the stm32h7r/s mcu
FRASTM May 31, 2024
15bcfb6
drivers: flash: stm32 xspi flash driver set the DelayBlock if exists
FRASTM May 6, 2025
09493b9
drivers: clock control: stm32H7RS has a PLL2 & 3 or HCLK5 output
FRASTM Apr 3, 2025
c2ddf9f
dts: arm: stm32h7rs mcu with external memory area
FRASTM May 30, 2024
e7a1f50
boards: st: stm32h7s3l8 nucleo board supporting xspi instance
FRASTM Nov 18, 2024
20adb4b
boards: arm: stm32h7s78 disco kit supporting xspi instance
FRASTM May 27, 2024
File filter

Filter by extension

Filter by extension
Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
72 changes: 72 additions & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -85,6 +85,19 @@
status = "okay";
};

/* PLL2 for clocking the xspi peripheral */
&pll2 {
div-m = <12>;
mul-n = <200>;
div-p = <2>;
div-q = <2>;
div-r = <2>;
div-s = <2>;
div-t = <2>;
clocks = <&clk_hse>;
status = "okay";
};

&rcc {
clocks = <&pll>;
clock-frequency = <DT_FREQ_M(200)>;
Expand Down Expand Up @@ -139,3 +152,62 @@
status = "okay";
clock-frequency = <I2C_BITRATE_FAST>;
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/* Set the partitions with first MB to make use of the whole Bank1 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
};
};

&xspi2 {
pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1
&xspim_p2_io0_pn2 &xspim_p2_io1_pn3
&xspim_p2_io2_pn4 &xspim_p2_io3_pn5
&xspim_p2_io4_pn8 &xspim_p2_io5_pn9
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11
&xspim_p2_dqs0_pn0>;
pinctrl-names = "default";

status = "okay";

mx25uw25645: xspi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0>;
size = <DT_SIZE_M(256)>; /* 256Mbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
status = "okay";

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 DT_SIZE_K(512)>;
};
Copy link
Contributor

@etienne-lms etienne-lms May 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Prefer with an empty line before each subnodes.

slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0080000 DT_SIZE_K(512)>;
};
scratch_partition: partition@100000 {
label = "image-scratch";
reg = <0x00100000 DT_SIZE_K(64)>;
};
storage_partition: partition@110000 {
label = "storage";
reg = <0x00110000 DT_SIZE_K(64)>;
Copy link
Contributor

@etienne-lms etienne-lms May 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Intentionally waste the remaining of the internal flash? 64kB is not much. Maybe increase to 1 or 2 MByte, or even (DT_SIZE_M(30) - DT_SIZE_K(64)).

};
};
};
};
1 change: 1 addition & 0 deletions boards/st/nucleo_h7s3l8/nucleo_h7s3l8.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -12,4 +12,5 @@ supported:
- watchdog
- entropy
- adc
- octospi
vendor: st
59 changes: 59 additions & 0 deletions boards/st/stm32h7s78_dk/stm32h7s78_dk.dts
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -207,6 +207,65 @@
};
};

&flash0 {
partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

/* Set the partitions with first MB to make use of the whole Bank1 */
boot_partition: partition@0 {
label = "mcuboot";
reg = <0x00000000 DT_SIZE_K(64)>;
};
};
};

&xspi2 {
pinctrl-0 = <&xspim_p2_clk_pn6 &xspim_p2_ncs1_pn1
&xspim_p2_io0_pn2 &xspim_p2_io1_pn3
&xspim_p2_io2_pn4 &xspim_p2_io3_pn5
&xspim_p2_io4_pn8 &xspim_p2_io5_pn9
&xspim_p2_io6_pn10 &xspim_p2_io7_pn11
&xspim_p2_dqs0_pn0>;
pinctrl-names = "default";

status = "okay";

mx66uw1g45: xspi-nor-flash@0 {
compatible = "st,stm32-xspi-nor";
reg = <0>;
size = <DT_SIZE_M(1024)>; /* 1 Gbits */
ospi-max-frequency = <DT_FREQ_M(50)>;
spi-bus-width = <XSPI_OCTO_MODE>;
data-rate = <XSPI_DTR_TRANSFER>;
status = "okay";

partitions {
compatible = "fixed-partitions";
#address-cells = <1>;
#size-cells = <1>;

slot0_partition: partition@0 {
label = "image-0";
reg = <0x00000000 DT_SIZE_K(512)>;
};
Copy link
Contributor

@etienne-lms etienne-lms May 21, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

Add an empty line between each subnode.

slot1_partition: partition@80000 {
label = "image-1";
reg = <0x0080000 DT_SIZE_K(512)>;
};
scratch_partition: partition@100000 {
label = "image-scratch";
reg = <0x00100000 DT_SIZE_K(64)>;
};
storage_partition: partition@110000 {
label = "storage";
reg = <0x00110000 DT_SIZE_K(64)>;
};
};
};
};

&die_temp {
status = "okay";
};
Expand Down
2 changes: 1 addition & 1 deletion boards/st/stm32h7s78_dk/stm32h7s78_dk.yaml
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -13,7 +13,7 @@ supported:
- watchdog
- entropy
- adc
- usb_device
- octospi
- usbd
- memc
vendor: st
20 changes: 19 additions & 1 deletion drivers/clock_control/clock_stm32_ll_h7.c
View file
Open in desktop
Original file line number Diff line number Diff line change
Expand Up @@ -337,6 +337,16 @@ int enabled_clock(uint32_t src_clk)
((src_clk == STM32_SRC_PLL2_R) && IS_ENABLED(STM32_PLL2_R_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_P) && IS_ENABLED(STM32_PLL3_P_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_Q) && IS_ENABLED(STM32_PLL3_Q_ENABLED)) ||
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
(src_clk == STM32_SRC_HCLK1) ||
(src_clk == STM32_SRC_HCLK2) ||
(src_clk == STM32_SRC_HCLK3) ||
(src_clk == STM32_SRC_HCLK4) ||
(src_clk == STM32_SRC_HCLK5) ||
((src_clk == STM32_SRC_PLL2_S) && IS_ENABLED(STM32_PLL2_S_ENABLED)) ||
((src_clk == STM32_SRC_PLL2_T) && IS_ENABLED(STM32_PLL2_T_ENABLED)) ||
((src_clk == STM32_SRC_PLL3_S) && IS_ENABLED(STM32_PLL3_S_ENABLED)) ||
#endif
((src_clk == STM32_SRC_PLL3_R) && IS_ENABLED(STM32_PLL3_R_ENABLED))) {
return 0;
}
Expand Down Expand Up @@ -460,6 +470,14 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
case STM32_CLOCK_BUS_AHB2:
case STM32_CLOCK_BUS_AHB3:
case STM32_CLOCK_BUS_AHB4:
#if defined(CONFIG_SOC_SERIES_STM32H7RSX)
/* HCLKn is a possible source clock for some peripherals */
case STM32_SRC_HCLK1:
case STM32_SRC_HCLK2:
case STM32_SRC_HCLK3:
case STM32_SRC_HCLK4:
case STM32_SRC_HCLK5:
Copy link
Contributor

@gautierg-st gautierg-st Apr 23, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

STM32_SRC_HCLK1/2/3/4 (added in the previous commit) and STM32_CLOCK_BUS_AHB5 should also be added here.

Copy link
Contributor Author

@FRASTM FRASTM Apr 24, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

moved to the other commit

Copy link
Contributor

@gautierg-st gautierg-st May 19, 2025

Choose a reason for hiding this comment

The reason will be displayed to describe this comment to others. Learn more.

STM32_SRC_HCLK1/2/3/4 and STM32_CLOCK_BUS_AHB5 cases are still missing in this function.

#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
*rate = ahb_clock;
break;
case STM32_CLOCK_BUS_APB1:
Expand Down Expand Up @@ -544,7 +562,7 @@ static int stm32_clock_control_get_subsys_rate(const struct device *clock,
STM32_PLL_N_MULTIPLIER,
STM32_PLL_S_DIVISOR);
break;
/* PLL 1 has no T-divider */
/* PLL 1 has no T-divider */
#endif /* CONFIG_SOC_SERIES_STM32H7RSX */
#endif /* STM32_PLL_ENABLED */
#if defined(STM32_PLL2_ENABLED)
Expand Down
Loading