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@FRASTM FRASTM commented Apr 15, 2025

This PR is for fixing the #88404 for the XSPI compatible

It changes the way the "st,stm32-xspi-nor" compatible declares the external flash base address and size.

The "st,stm32-xspi" node, gives the external memory base address and maximum allocated space (in bytes):

		xspi1: spi@47001400 {
			compatible = "st,stm32-xspi";
			reg = <0x47001400 0x400>, <0x90000000 0x10000000>;

The "st,stm32-xspi-nor" node, gives the external NOR device size in Bits through the size property

	mx25lm51245: ospi-nor-flash@0 {
		compatible = "st,stm32-xspi-nor";
		reg = <0>;
		size = <0x20000000>; /* 512 Mbits */

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FRASTM commented Apr 15, 2025

No warning during west build -b stm32h573i_dk samples/application_development/code_relocation_nocopy

*** Booting Zephyr OS build v4.1.0-2355-g18aeeafb96ea ***
Address of main function 0x80005e1
Address of function_in_ext_flash 0x90000001
Address of var_ext_sram_data 0x200000a0 (10)
Address of function_in_sram 0x20000001
Address of var_sram_data 0x200000a4 (10)
Hello World! stm32h573i_dk

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Please update migration guide, as this change will break out of tree users.

@FRASTM FRASTM force-pushed the xspi_dts branch 2 times, most recently from 80bb911 to 0d2c8d4 Compare April 16, 2025 07:19
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FRASTM commented Apr 16, 2025

Adding text for the doc: release-notes-4-2:

@github-actions github-actions bot added the Release Notes To be mentioned in the release notes label Apr 16, 2025
@github-actions github-actions bot requested a review from fabiobaltieri April 16, 2025 07:37
@rruuaanng rruuaanng linked an issue Apr 16, 2025 that may be closed by this pull request
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If possible, making multiple commits in this PR could help reduce email noise :)

fabiobaltieri
fabiobaltieri previously approved these changes Apr 16, 2025
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FRASTM commented Apr 25, 2025

ci failure : #89081

@erwango erwango removed the block: HW Test Testing on hardware required before merging label Apr 30, 2025
FRASTM added 10 commits April 30, 2025 15:01
This PR adds the size in Bits of the flash nor memory
for the st,stm32-xspi-nor compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This PR adds the size in Bits of the PSRAM  memory
for the st,stm32-xspi-psram compatible

Signed-off-by: Francois Ramu <francois.ramu@st.com>
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
size. For the stm32N6 serie,
xspi1 is addressing max 256 MBytes from 0x90000000
xspi2 is addressing max 256 MBytes from 0x70000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
The st,stm32-xspi compatible is defining the reg property
with the register address and size at first index
followed by the external memory base address and max allocated
xspi1 is addressing max 256 MBytes from 0x90000000

Signed-off-by: Francois Ramu <francois.ramu@st.com>
New property of the st,stm32-xspi-nor compatible gives
the external NOR flash in bits.
The property of the st,stm32-xspi compatible gives
the external NOR flash base address

Signed-off-by: Francois Ramu <francois.ramu@st.com>
New property of the st,stm32-xspi-psram compatible gives
the external PSRAM memory in bits.
The property of the st,stm32-xspi compatible gives
the external PSRAM memory base address

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This PR defines the "st,stm32-xspi-nor" compatible Node
and the "st,stm32-xspi-psram" compatible Node
in conformance to the DTS specifications
Includes the size property (in Bits) of the external memory device

Signed-off-by: Francois Ramu <francois.ramu@st.com>
This PR defines the "st,stm32-xspi-nor" compatible Node
in conformance to the DTS specifications
Includes the size property (in Bits) of the external NOR device

Signed-off-by: Francois Ramu <francois.ramu@st.com>
In case of the st,stm32-xspi-nor compatible
new property and node definitions will requires new macro
to get the external NOR flash base address and size

Signed-off-by: Francois Ramu <francois.ramu@st.com>
Change to apply on the DTS of STM32 soc and boards with xSPI nodes

Signed-off-by: Francois Ramu <francois.ramu@st.com>
@kartben kartben merged commit 22ca514 into zephyrproject-rtos:main Apr 30, 2025
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stm32: q/o/x-spi bindings generate dtc warnings

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