drivers: i2s: add sai support for stm32h7rs

dts/arm/st/h7rs/stm32h7rs.dtsi

@@ -1,5 +1,6 @@
 /*
  * Copyright (c) 2024 STMicroelectronics
+ * Copyright (c) 2025 Mario Paja
  *
  * SPDX-License-Identifier: Apache-2.0
  */
@@ -16,6 +17,7 @@
 #include <zephyr/dt-bindings/memory-attr/memory-attr.h>
 #include <zephyr/dt-bindings/memory-attr/memory-attr-arm.h>
 #include <zephyr/dt-bindings/flash_controller/xspi.h>
+#include <zephyr/dt-bindings/dma/stm32_dma.h>
 #include <freq.h>
 
 /*
@@ -814,6 +816,43 @@
 				 <&rcc STM32_SRC_HSI48 OTGFS_SEL(0)>;
 			status = "disabled";
 		};
+
+		gpdma1: dma@40021000 {
+			compatible = "st,stm32u5-dma";
+			#dma-cells = <3>;
+			reg = <0x40021000 0x1000>;
+			clocks = <&rcc STM32_CLOCK(AHB1, 4)>;
+			interrupts = <39 0 40 0 41 0 42 0 43 0 44 0 45 0 46 0
+				      133 0 134 0 135 0 136 0 137 0 138 0 139 0 140 0>;
+			dma-channels = <16>;
+			dma-requests = <109>;
+			dma-offset = <0>;
+			status = "disabled";
+		};
+
+		sai1_a: sai1@42005804 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x42005804 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 22)>,
+				 <&rcc STM32_SRC_PLL3_P SAI1_SEL(2)>;
+			dmas = <&gpdma1 1 63 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+				STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
+
+		sai1_b: sai1@42005824 {
+			compatible = "st,stm32-sai";
+			#address-cells = <1>;
+			#size-cells = <0>;
+			reg = <0x42005824 0x20>;
+			clocks = <&rcc STM32_CLOCK(APB2, 22)>,
+				 <&rcc STM32_SRC_PLL3_P SAI1_SEL(2)>;
+			dmas = <&gpdma1 0 64 (STM32_DMA_MODE_NORMAL | STM32_DMA_PRIORITY_HIGH |
+				STM32_DMA_16BITS)>;
+			status = "disabled";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {

samples/drivers/i2s/output/boards/nucleo_h7s3l8.conf

@@ -0,0 +1 @@
+CONFIG_HEAP_MEM_POOL_SIZE=4192

samples/drivers/i2s/output/boards/nucleo_h7s3l8.overlay

@@ -0,0 +1,39 @@
+/*
+ * Copyright (c) 2025 Mario Paja
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+/ {
+	aliases {
+		i2s-tx = &sai1_a;
+	};
+};
+
+/* PLL3 for clocking SAI1 peripheral */
+&pll3 {
+	/* 44.1KHz (-0.1% Error) */
+	div-m = <12>;
+	mul-n = <203>;
+	div-p = <2>;
+	div-q = <2>;
+	div-r = <2>;
+	div-s = <2>;
+	div-t = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
+&sai1_a {
+	pinctrl-0 = <&sai1_mclk_a_pg7 &sai1_sd_a_pc1
+		&sai1_fs_a_pe4 &sai1_sck_a_pe5>;
+	pinctrl-names = "default";
+	status = "okay";
+	mclk-enable;
+	mclk-divider = "div-256";
+	dma-names = "tx";
+};
+
+&gpdma1 {
+	status = "okay";
+};