Enable display / ltdc on the stm32h7s78 dk board

boards/st/stm32h7s78_dk/Kconfig.defconfig

@@ -14,4 +14,21 @@ config NET_L2_ETHERNET
 
 endif # NETWORKING
 
+if DISPLAY
+# MEMC needs to be enabled in order to store
+# display frame buffer to external PSRAM
+config MEMC
+	default y
+
+# Rely on Multi-Heap / Shared-Multi-Heap for PSRAM access
+config MULTI_HEAP
+	default y
+config SHARED_MULTI_HEAP
+	default y
+
+# Let LTDC use memory allocated via SMH
+config STM32_LTDC_FB_USE_SHARED_MULTI_HEAP
+	default y
+endif # DISPLAY
+
 endif # BOARD_STM32H7S78_DK

boards/st/stm32h7s78_dk/stm32h7s78_dk.dts

@@ -8,6 +8,7 @@
 #include <st/h7rs/stm32h7s7X8.dtsi>
 #include <st/h7/stm32h7s7l8hxh-pinctrl.dtsi>
 #include "arduino_r3_connector.dtsi"
+#include "zephyr/dt-bindings/display/panel.h"
 #include <zephyr/dt-bindings/input/input-event-codes.h>
 
 / {
@@ -19,6 +20,7 @@
 		zephyr,shell-uart = &uart4;
 		zephyr,flash = &flash0;
 		zephyr,sram = &sram0;
+		zephyr,display = &ltdc;
 	};
 
 	psram: memory@90000000 {
@@ -107,6 +109,14 @@
 	status = "okay";
 };
 
+&pll3 {
+	div-m = <12>;
+	mul-n = <25>;
+	div-r = <2>;
+	clocks = <&clk_hse>;
+	status = "okay";
+};
+
 &rcc {
 	clocks = <&pll>;
 	clock-frequency = <DT_FREQ_M(250)>;
@@ -304,3 +314,40 @@ usb2: &usbotg_fs {
 };
 
 zephyr_udc0: &usb2 {};
+
+&ltdc {
+	pinctrl-0 = <&ltdc_r0_pf9 &ltdc_r1_pf10 &ltdc_r2_pf0 &ltdc_r3_pb4
+		     &ltdc_r4_pb3 &ltdc_r5_pa15 &ltdc_r6_pg1 &ltdc_r7_pg0
+		     &ltdc_g0_pf7 &ltdc_g1_pf15 &ltdc_g2_pa1 &ltdc_g3_pa0
+		     &ltdc_g4_pb13 &ltdc_g5_pb12 &ltdc_g6_pb11 &ltdc_g7_pb15
+		     &ltdc_b0_pf11 &ltdc_b1_pg14 &ltdc_b2_pa12 &ltdc_b3_pa11
+		     &ltdc_b4_pa10 &ltdc_b5_pa9 &ltdc_b6_pa8 &ltdc_b7_pa6
+		     &ltdc_de_pb14 &ltdc_clk_pg13 &ltdc_hsync_pg2 &ltdc_vsync_pe11>;
+	pinctrl-names = "default";
+	disp-on-gpios = <&gpioe 15 GPIO_ACTIVE_HIGH>;
+	bl-ctrl-gpios = <&gpiog 15 GPIO_ACTIVE_HIGH>;
+
+	status = "okay";
+
+	width = <800>;
+	height = <480>;
+	pixel-format = <PANEL_PIXEL_FORMAT_RGB_565>;
+
+	display-timings {
+		compatible = "zephyr,panel-timing";
+		de-active = <0>;
+		pixelclk-active = <0>;
+		hsync-active = <0>;
+		vsync-active = <0>;
+		hsync-len = <4>;
+		vsync-len = <4>;
+		hback-porch = <8>;
+		vback-porch = <8>;
+		hfront-porch = <8>;
+		vfront-porch = <8>;
+	};
+
+	def-back-color-red = <0xFF>;
+	def-back-color-green = <0xFF>;
+	def-back-color-blue = <0xFF>;
+};

boards/st/stm32h7s78_dk/stm32h7s78_dk_defconfig

@@ -18,3 +18,10 @@ CONFIG_UART_CONSOLE=y
 
 # enable GPIO
 CONFIG_GPIO=y
+
+# SRAM0 being small (128KB), SYS_HEAP_SMALL_ONLY
+# is automatically selected, leading to not being
+# able to tackle HEAP on the large PSRAM. Force it
+# to AUTO in order to be able to handle HEAP on
+# both SRAM and PSRAM
+CONFIG_SYS_HEAP_AUTO=y

dts/arm/st/h7rs/stm32h7rs.dtsi

@@ -897,6 +897,17 @@
 				STM32_DMA_16BITS)>;
 			status = "disabled";
 		};
+
+		ltdc: ltdc@50001000 {
+			compatible = "st,stm32-ltdc";
+			reg = <0x50001000 0x400>;
+			interrupts = <96 0>, <97 0>;
+			interrupt-names = "ltdc", "ltdc_er";
+			clocks = <&rcc STM32_CLOCK(APB5, 1)>,
+				 <&rcc STM32_SRC_PLL3_R NO_SEL>;
+			resets = <&rctl STM32_RESET(APB5, 1)>;
+			status = "disabled";
+		};
 	};
 
 	otgfs_phy: otgfs_phy {

samples/drivers/display/boards/stm32h7s78_dk.conf

@@ -0,0 +1,6 @@
+# Copyright (c) 2025 STMicroelectronics
+# SPDX-License-Identifier: Apache-2.0
+
+# On STM32H7S78 DK board, display being larger, it requires
+# more memory to draw squares on the display (40K)
+CONFIG_HEAP_MEM_POOL_SIZE=65536

soc/st/stm32/stm32h7rsx/CMakeLists.txt

@@ -5,6 +5,8 @@ zephyr_sources(
   soc.c
   )
 
+zephyr_sources(mpu_regions.c)
+
 zephyr_include_directories(.)
 
 set(SOC_LINKER_SCRIPT ${ZEPHYR_BASE}/include/zephyr/arch/arm/cortex_m/scripts/linker.ld CACHE INTERNAL "")

soc/st/stm32/stm32h7rsx/Kconfig

@@ -11,6 +11,7 @@ config SOC_SERIES_STM32H7RSX
 	select HAS_STM32CUBE
 	select CPU_HAS_ARM_MPU
 	select HAS_SWO
+	select CPU_HAS_CUSTOM_FIXED_SOC_MPU_REGIONS
 	select CPU_HAS_FPU_DOUBLE_PRECISION
 	select CPU_HAS_ICACHE
 	select CPU_HAS_DCACHE

soc/st/stm32/stm32h7rsx/mpu_regions.c

@@ -0,0 +1,34 @@
+/*
+ * Copyright (c) 2017 Linaro Limited.
+ * Copyright (c) 2025 STMicroelectronics
+ *
+ * SPDX-License-Identifier: Apache-2.0
+ */
+
+#include <zephyr/sys/slist.h>
+#include <zephyr/arch/arm/mpu/arm_mpu.h>
+
+#include <zephyr/arch/arm/cortex_m/arm_mpu_mem_cfg.h>
+
+static const struct arm_mpu_region mpu_regions[] = {
+	/* Use first region to prevent speculative access in entire memory space */
+	/* Region 0 */
+	MPU_REGION_ENTRY("UNMAPPED", 0, {REGION_4G | MPU_RASR_XN_Msk | P_NA_U_NA_Msk}),
+
+	/* Region 1 */
+	MPU_REGION_ENTRY("PERIPH", 0x40000000, REGION_IO_ATTR(REGION_512M)),
+
+#ifdef CONFIG_XIP
+	/* Region 2 */
+	MPU_REGION_ENTRY("FLASH_0", CONFIG_FLASH_BASE_ADDRESS,
+			 REGION_FLASH_ATTR(REGION_FLASH_SIZE)),
+#endif
+
+	/* Region 3 */
+	MPU_REGION_ENTRY("SRAM_0", CONFIG_SRAM_BASE_ADDRESS, REGION_RAM_ATTR(REGION_SRAM_SIZE)),
+};
+
+const struct arm_mpu_config mpu_config = {
+	.num_regions = ARRAY_SIZE(mpu_regions),
+	.mpu_regions = mpu_regions,
+};