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LLVM 14 regression: std.leb128 miscompilation on riscv64 #12031

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andrewrk opened this issue Jul 7, 2022 · 1 comment · Fixed by #13953
Closed

LLVM 14 regression: std.leb128 miscompilation on riscv64 #12031

andrewrk opened this issue Jul 7, 2022 · 1 comment · Fixed by #13953
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arch-riscv 32-bit and 64-bit RISC-V backend-llvm The LLVM backend outputs an LLVM IR Module. bug Observed behavior contradicts documented or intended behavior contributor friendly This issue is limited in scope and/or knowledge of Zig internals. miscompilation The compiler reports success but produces semantically incorrect code. regression It worked in a previous version of Zig, but stopped working. upstream An issue with a third party project that Zig uses.
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@andrewrk
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andrewrk commented Jul 7, 2022

Zig Version: 0.10.0-dev.2896+fa40bddf2

Reproduce:

$ stage1/bin/zig test ../lib/std/std.zig -target riscv64-linux-none
Test [541/2199] leb128.test "std-riscv64-linux-none-Debug-bare-multi-default serialize ... FAIL (TestUnexpectedResult)
/home/andy/dev/zig/lib/std/leb128.zig:333:5: 0x57fb47 in leb128.test_write_leb128 (test)
    try testing.expect(w1_pos == bytes_needed);
    ^
Test [542/2199] leb128.test "std-riscv64-linux-none-Debug-bare-multi-default serialize ... FAIL (TestUnexpectedResult)
/home/andy/dev/zig/lib/std/leb128.zig:333:5: 0x57fb47 in leb128.test_write_leb128 (test)
    try testing.expect(w1_pos == bytes_needed);
    ^
2127 passed; 70 skipped; 2 failed.
error: the following test command failed with exit code 1:
qemu-riscv64 /home/andy/dev/zig/zig-cache/o/58c985004802103d620615fe2c55895a/test /home/andy/dev/zig/build-llvm14-debug/stage1/bin/zig
test...The following command exited with error code 1:
/home/andy/dev/zig/build-llvm14-debug/stage1/bin/zig test /home/andy/dev/zig/lib/std/std.zig --test-name-prefix std-riscv64-linux-none-Debug-bare-multi-default  --cache-dir /home/andy/dev/zig/zig-cache --global-cache-dir /home/andy/.cache/zig --name test -fno-single-threaded -target riscv64-linux-none -mcpu baseline_rv64 --test-cmd qemu-riscv64 --test-cmd-bin -I /home/andy/dev/zig/test -L /home/andy/local/llvm14-debug/lib -isystem /home/andy/local/llvm14-debug/include --zig-lib-dir /home/andy/dev/zig/lib --enable-cache 

Failing test cases:

zig/lib/std/leb128.zig

Lines 348 to 378 in aab1284

test "serialize unsigned LEB128" {
const max_bits = 18;
comptime var t = 0;
inline while (t <= max_bits) : (t += 1) {
const T = std.meta.Int(.unsigned, t);
const min = std.math.minInt(T);
const max = std.math.maxInt(T);
var i = @as(std.meta.Int(.unsigned, @typeInfo(T).Int.bits + 1), min);
while (i <= max) : (i += 1) try test_write_leb128(@intCast(T, i));
}
}
test "serialize signed LEB128" {
// explicitly test i0 because starting `t` at 0
// will break the while loop
try test_write_leb128(@as(i0, 0));
const max_bits = 18;
comptime var t = 1;
inline while (t <= max_bits) : (t += 1) {
const T = std.meta.Int(.signed, t);
const min = std.math.minInt(T);
const max = std.math.maxInt(T);
var i = @as(std.meta.Int(.signed, @typeInfo(T).Int.bits + 1), min);
while (i <= max) : (i += 1) try test_write_leb128(@intCast(T, i));
}
}

Next steps:

  1. Create LLVM IR test case
  2. Use llvm-reduce to create reduction
  3. Check if bug is present on trunk
  4. File upstream bug report
@andrewrk andrewrk added bug Observed behavior contradicts documented or intended behavior contributor friendly This issue is limited in scope and/or knowledge of Zig internals. upstream An issue with a third party project that Zig uses. miscompilation The compiler reports success but produces semantically incorrect code. arch-riscv 32-bit and 64-bit RISC-V backend-llvm The LLVM backend outputs an LLVM IR Module. regression It worked in a previous version of Zig, but stopped working. labels Jul 7, 2022
@andrewrk andrewrk added this to the 0.11.0 milestone Jul 7, 2022
@topolarity
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fn foo() void { }

test {
    var value = @as(u15, 0x4000); 
    _ = foo();
    if (@clz(u15, value) != 0) unreachable;
}

Does not reproduce on Zig 0.9.1 or current Zig master (with LLVM 13).

Reproduces with LLVM 14.0.5 and trunk. LLVM bug filed here: llvm/llvm-project#56457

wooster0 pushed a commit to wooster0/zig that referenced this issue Jul 24, 2022
Ivan-Velickovic added a commit to Ivan-Velickovic/zig that referenced this issue Dec 15, 2022
These were previously disabled due to an LLVM 14 regression, see
ziglang#12031 for more details. This has been fixed
in LLVM 15.
Ivan-Velickovic added a commit to Ivan-Velickovic/zig that referenced this issue Dec 15, 2022
These were previously disabled due to a LLVM 14 regression, see
ziglang#12031 for more details. This has been fixed
in LLVM 15.
andrewrk pushed a commit that referenced this issue Dec 15, 2022
These were previously disabled due to a LLVM 14 regression, see
#12031 for more details. This has been fixed
in LLVM 15.
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Labels
arch-riscv 32-bit and 64-bit RISC-V backend-llvm The LLVM backend outputs an LLVM IR Module. bug Observed behavior contradicts documented or intended behavior contributor friendly This issue is limited in scope and/or knowledge of Zig internals. miscompilation The compiler reports success but produces semantically incorrect code. regression It worked in a previous version of Zig, but stopped working. upstream An issue with a third party project that Zig uses.
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