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std.crypto.chacha: support larger vectors on AVX2 and AVX512 targets #15809

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merged 2 commits into from
May 22, 2023

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@jedisct1 jedisct1 commented May 21, 2023

Ryzen 7 7700, ChaCha20/8 stream, long outputs:

Generic: 3268 MiB/s
AVX2   : 6023 MiB/s
AVX512 : 8086 MiB/s

Apple M1 CPUs seem to also benefit from a 4-way implementation on micro-benchmarks, but only on full-round ChaCha, and I'm not sure we can generalize it to other aarch64 CPUs, or to real workloads.

So, enable this only on x86_64 for now. verified to also improve performance on a Cortex A72, so enabling on aarch64, too.

Bump the rand.chacha buffer a tiny bit to take advantage of this. More than 8 blocks doesn't seem to make any measurable difference.

ChaChaPoly also gets a small performance boost from this, albeit Poly1305 remains the bottleneck.

Generic:  707 MiB/s
AVX2   :  981 MiB/s
AVX512 : 1202 MiB/s

jedisct1 added 2 commits May 22, 2023 00:45
Ryzen 7 7700, ChaCha20/8 stream, long outputs:

Generic: 3268 MiB/s
AVX2   : 6023 MiB/s
AVX512 : 8086 MiB/s

Apple M1 CPUs seem to also benefit from a 4-way implementation on
micro-benchmarks, but only on full-round ChaCha, and I'm not sure
we can generalize it to other aarch64 CPUs, or to real workloads.

So, enable this only on x86_64 for now.

Bump the rand.chacha buffer a tiny bit to take advantage of this.
More than 8 blocks doesn't seem to make any measurable difference.

ChaChaPoly also gets a small performance boost from this, albeit
Poly1305 remains the bottleneck.

Generic:  707 MiB/s
AVX2   :  981 MiB/s
AVX512 : 1202 MiB/s
Verified on Apple Silicon, but also on a Cortex A72.
@jedisct1 jedisct1 added the standard library This issue involves writing Zig code for the standard library. label May 22, 2023
@jedisct1 jedisct1 merged commit 5af89b3 into ziglang:master May 22, 2023
@jedisct1 jedisct1 deleted the chacha-vec-2-4 branch May 22, 2023 18:46
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2 participants