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Merge pull request #277 from openpassport-org/fix/zkemail-rsa
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Fix/zkemail rsa
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@remicolin
remicolin authored Dec 27, 2024
2 parents c5045f2 + 62528b1 commit 22bc01e
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Showing 36 changed files with 2,037 additions and 251 deletions.
Binary file modified circuits/.yarn/install-state.gz
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2 changes: 1 addition & 1 deletion circuits/circuits/dsc/instances/dsc_rsa_sha256_65537_4096.circom
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Expand Up @@ -2,4 +2,4 @@ pragma circom 2.1.9;

include "../openpassport_dsc.circom";

component main { public [ merkle_root ] } = OPENPASSPORT_DSC(10, 64, 32, 64, 64, 1664, 256, 12);
component main { public [ merkle_root ] } = OPENPASSPORT_DSC(10, 64, 32, 120, 35, 1664, 256, 12);
5 changes: 2 additions & 3 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha1_65537_2048.circom
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@@ -1,14 +1,13 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa65537Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[32];
signal input modulus[32];
signal input message[32];


VerifyRsaPkcs1v1_5(3, 64, 32, 65537, 160)(signature, modulus, message);
VerifyRsa65537Pkcs1v1_5(64, 32, 160)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
5 changes: 2 additions & 3 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha256_3_2048.circom
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@@ -1,14 +1,13 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa3Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[32];
signal input modulus[32];
signal input message[32];


VerifyRsaPkcs1v1_5(13, 64, 32, 3, 256)(signature, modulus, message);
VerifyRsa3Pkcs1v1_5(64, 32, 256)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
4 changes: 2 additions & 2 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha256_65537_2048.circom
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@@ -1,14 +1,14 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa65537Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[32];
signal input modulus[32];
signal input message[32];


VerifyRsaPkcs1v1_5(1, 64, 32, 65537, 256)(signature, modulus, message);
VerifyRsa65537Pkcs1v1_5(64, 32, 256)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
5 changes: 2 additions & 3 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha256_65537_3072.circom
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@@ -1,14 +1,13 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa65537Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[32];
signal input modulus[32];
signal input message[32];


VerifyRsaPkcs1v1_5(14, 96, 32, 65537, 256)(signature, modulus, message);
VerifyRsa65537Pkcs1v1_5(96, 32, 256)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
11 changes: 5 additions & 6 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha256_65537_4096.circom
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@@ -1,14 +1,13 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa65537Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[64];
signal input modulus[64];
signal input message[64];
signal input signature[35];
signal input modulus[35];
signal input message[35];


VerifyRsaPkcs1v1_5(10, 64, 64, 65537, 256)(signature, modulus, message);
VerifyRsa65537Pkcs1v1_5(120, 35, 256)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
11 changes: 5 additions & 6 deletions circuits/circuits/tests/utils/rsa/test_rsa_sha512_65537_4096.circom
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@@ -1,14 +1,13 @@
pragma circom 2.1.9;

include "../../../utils/circomlib/signature/rsa/verifyRsaPkcs1v1_5.circom";
include "../../../utils/circomlib/signature/rsa/verifyRsa65537Pkcs1v1_5.circom";

template VerifyRsaPkcs1v1_5Tester() {
signal input signature[64];
signal input modulus[64];
signal input message[64];
signal input signature[35];
signal input modulus[35];
signal input message[35];


VerifyRsaPkcs1v1_5(15, 64, 64, 65537, 512)(signature, modulus, message);
VerifyRsa65537Pkcs1v1_5(120, 35, 512)(signature, modulus, message);
}

component main = VerifyRsaPkcs1v1_5Tester();
14 changes: 7 additions & 7 deletions circuits/circuits/utils/circomlib/bigInt/bigInt.circom
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Expand Up @@ -236,7 +236,7 @@ template BigMod(CHUNK_SIZE, CHUNK_NUMBER){
signal input base[CHUNK_NUMBER * 2];
signal input modulus[CHUNK_NUMBER];

var long_division[2][200] = long_div(CHUNK_SIZE, CHUNK_NUMBER, CHUNK_NUMBER, base, modulus);
var long_division[2][200] = long_div_dl(CHUNK_SIZE, CHUNK_NUMBER, CHUNK_NUMBER, base, modulus);

signal output div[CHUNK_NUMBER + 1];
signal output mod[CHUNK_NUMBER];
Expand Down Expand Up @@ -366,7 +366,7 @@ template PowerMod(CHUNK_SIZE, CHUNK_NUMBER, EXP) {

signal output out[CHUNK_NUMBER];

var exp_process[256] = exp_to_bits(EXP);
var exp_process[256] = exp_to_bits_dl(EXP);

component muls[exp_process[0]];
component resultMuls[exp_process[1] - 1];
Expand Down Expand Up @@ -422,7 +422,7 @@ template BigModInvOptimised(CHUNK_SIZE, CHUNK_NUMBER) {
signal output out[CHUNK_NUMBER];


var inv[200] = mod_inv(CHUNK_SIZE, CHUNK_NUMBER, in, modulus);
var inv[200] = mod_inv_dl(CHUNK_SIZE, CHUNK_NUMBER, in, modulus);
for (var i = 0; i < CHUNK_NUMBER; i++) {
out[i] <-- inv[i];
}
Expand Down Expand Up @@ -642,7 +642,7 @@ template BigModNonEqual(CHUNK_SIZE, CHUNK_NUMBER_BASE, CHUNK_NUMBER_MODULUS){
signal input base[CHUNK_NUMBER_BASE];
signal input modulus[CHUNK_NUMBER_MODULUS];

var long_division[2][200] = long_div(CHUNK_SIZE, CHUNK_NUMBER_MODULUS, CHUNK_NUMBER_DIV - 1, base, modulus);
var long_division[2][200] = long_div_dl(CHUNK_SIZE, CHUNK_NUMBER_MODULUS, CHUNK_NUMBER_DIV - 1, base, modulus);

signal output div[CHUNK_NUMBER_DIV];
signal output mod[CHUNK_NUMBER_MODULUS];
Expand Down Expand Up @@ -759,7 +759,7 @@ template PowerModNonOptimised(CHUNK_SIZE, CHUNK_NUMBER, EXP) {

signal output out[CHUNK_NUMBER];

var exp_process[256] = exp_to_bits(EXP);
var exp_process[256] = exp_to_bits_dl(EXP);

component muls[exp_process[0]];
component resultMuls[exp_process[1] - 1];
Expand Down Expand Up @@ -814,7 +814,7 @@ template PowerModNonOptimised(CHUNK_SIZE, CHUNK_NUMBER, EXP) {
// those are very "expensive" by constraints operations, try to reduse num of usage if these if u can

// in[0] < in[1]
template BigLessThan(CHUNK_SIZE, CHUNK_NUMBER){
template BigLessThan_dl(CHUNK_SIZE, CHUNK_NUMBER){
signal input in[2][CHUNK_NUMBER];

signal output out;
Expand Down Expand Up @@ -892,7 +892,7 @@ template BigGreaterEqThan(CHUNK_SIZE, CHUNK_NUMBER){

signal output out;

component lessThan = BigLessThan(CHUNK_SIZE, CHUNK_NUMBER);
component lessThan = BigLessThan_dl(CHUNK_SIZE, CHUNK_NUMBER);
lessThan.in <== in;
out <== 1 - lessThan.out;
}
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