AMF-Placer 2.0: An Open-Source Timing-driven Analytical Mixed-size FPGA Placer

What's Changed

1. a set of timing optimization algorithms without involving static timing analysis (STA), e.g., path-length-aware SA-based floorplanning and parallelized CLB packing with timing factors considered.
2. an efficient piecewise regression model of pin-to-pin delay, utilized by our integrated lightweight parallelized timing analysis engine.
3. a placement-blockage-aware optimization scheme, which identifies the potential negative interference of placement blockage with long paths, spreads the instances in specific regions, and inserts placement anchors for the instances in the target paths to reduce cross-blockage routing.
4. a WNS-aware timing-driven global placement, based on quadratic programming and proper exploitation of pseudo-nets with slack-guided weights, which realizes the multi-objective optimization of WNS, TNS, and wirelength.
5. a sector-guided detailed placement algorithm, which can efficiently identify the instance movement with promising timing benefits. The timing can be comprehensively optimized by AMF-Placer~{2.0} at various granularity levels (i.e., multi-path, per-path, and per-instance).
6. A GUI for visualization of the placement procedure (zoom in / zoom out / critical path identification ...)