Project : Design and Implementation of FSM-based adder synchronized with clock in Verilog, Verifying it’s working through UVM Testbench.
This was made as the final project under the mentor assigned by NXP Semiconductors, under NXP Women in Tech program, We designed an FSM based adder and synchronised it with clock, in verilog and verified it's wprking through UVM Testbench the entire code was written on EDA Playground.