Skip to content
New issue

Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.

By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.

Already on GitHub? Sign in to your account

Add APX ISA extension #450

Open
wants to merge 58 commits into
base: master
Choose a base branch
from
Open
Show file tree
Hide file tree
Changes from 15 commits
Commits
Show all changes
58 commits
Select commit Hold shift + click to select a range
1ff1048
Add `AMX` ISA extension
flobernd Sep 12, 2023
e53326b
Decoding WiP
flobernd Sep 12, 2023
154b8da
rex2 progress
athre0z Sep 12, 2023
58ea163
APX progress
flobernd Sep 12, 2023
21726c2
APX progress
flobernd Sep 12, 2023
aef8cdf
Fix `movabs`/`jmpabs` instruction
flobernd Sep 13, 2023
2580411
APX progress
flobernd Sep 13, 2023
5c58f02
APX progress
flobernd Sep 13, 2023
e895846
APX progress
flobernd Sep 14, 2023
47d51b6
APX progress
flobernd Sep 14, 2023
0f21bbf
APX progress
flobernd Sep 28, 2023
a8c754f
Add `UD0_COMPAT` decoder mode
flobernd Jan 22, 2024
c422232
Merge remote-tracking branch 'remotes/origin/ud0-compat' into apx
flobernd Jan 22, 2024
b46eaa3
APX progress
flobernd Jan 23, 2024
d5c64bf
APX progress
flobernd Jan 23, 2024
09592fa
APX progress
flobernd Jan 25, 2024
b9e33d7
APX progress
flobernd Jan 25, 2024
0f1ad8b
APX progress
flobernd May 6, 2024
219e984
Allow 32 GPR registers with `rm` encoding
flobernd Sep 18, 2024
a272cd9
Fixed `scc` handling (#528)
mappzor Oct 16, 2024
09f2394
Temp
flobernd Oct 29, 2024
a5c5c33
Merge remote-tracking branch 'remotes/origin/master' into apx
flobernd Oct 29, 2024
7e0ec6f
Update instruction definitions
flobernd Oct 29, 2024
c105172
Add `ZYDIS_ATTRIB_HAS_EEVEX`
flobernd Oct 29, 2024
fa4db5c
Fixed MVEX tests (#529)
mappzor Oct 30, 2024
4db1608
Replace incorrect assertion
flobernd Oct 30, 2024
2031c37
Change operand size map to `force64` for `push2`/`pop2`
flobernd Oct 30, 2024
fa5240c
APX progress
flobernd Oct 30, 2024
fbf7c5c
Fix `EVEX.U` filters
flobernd Oct 30, 2024
46e87b9
Fix `EVEX.U` filters (take 2)
flobernd Oct 30, 2024
a80aa46
Move apx info
flobernd Oct 30, 2024
dce4de0
Add `uses_egpr` APX info
flobernd Oct 31, 2024
92bc5f5
Expose `dfv` in `apx` struct instead of operand
flobernd Oct 31, 2024
a89733e
Ignore `EVEX.U` filter for EVEX "legacy" instructions if APX mode is …
flobernd Oct 31, 2024
b279618
Do not trigger assertion for 0 byte (variable) memory operands
flobernd Nov 1, 2024
a5e1ccb
Mark APX AMX_TILE instructions as EEVEX
flobernd Nov 1, 2024
9ae3bfa
Minor fix
flobernd Nov 1, 2024
87c68a4
Fixed EGPR SIB.base handling (#532)
mappzor Nov 2, 2024
a13c171
Cleanup
flobernd Nov 2, 2024
7c1a34b
Wire `has_ppx` flag
flobernd Nov 2, 2024
6481300
Fix inverted condition
flobernd Nov 3, 2024
a5a6f61
APX formatter support
flobernd Nov 3, 2024
282bb95
Add missing push/pop variants
flobernd Nov 3, 2024
d8aee19
Second attempt
flobernd Nov 3, 2024
10cf4b3
Minor bugfixes
flobernd Nov 4, 2024
49a1ef4
Fix `jmpabs` prefix flags
flobernd Nov 4, 2024
21614ce
Remove hardcoded `no_rex2` condition
flobernd Nov 4, 2024
9ff14fa
Add TODO
flobernd Nov 4, 2024
544de93
Fix `rex2` filters
flobernd Nov 4, 2024
00383e0
Remove scaling of `xcrypt*` memory operands
flobernd Nov 5, 2024
0361fc0
Encoder: APX support (#533)
mappzor Nov 5, 2024
0e4a87e
Fix `vpcmp?str?` definitions
flobernd Nov 5, 2024
0848597
Regenerate encoder tables
flobernd Nov 5, 2024
58acf3c
Fix `has_egpr` flag
flobernd Nov 5, 2024
b8149e3
Fix `xsha1` and `xsha256` memory operand scaling
flobernd Nov 6, 2024
35509e1
Fixed `movdiri` (APX) and compressed disp8 handling (#536)
mappzor Nov 6, 2024
25eb33c
Fix `montmul` operand scaling
flobernd Nov 6, 2024
147a375
Removed `xsha1`/`xsha256` workaround (#537)
mappzor Nov 8, 2024
File filter

Filter by extension

Filter by extension

Conversations
Failed to load comments.
Loading
Jump to
Jump to file
Failed to load files.
Loading
Diff view
Diff view
2 changes: 1 addition & 1 deletion dependencies/zycore
Submodule zycore updated 1 files
+2 −2 LICENSE
3 changes: 2 additions & 1 deletion examples/ZydisPerfTest.c
Original file line number Diff line number Diff line change
Expand Up @@ -417,7 +417,8 @@ static void GenerateTestData(FILE* file, ZyanU8 encoding)
switch (encoding)
{
case 0:
b = (instruction.encoding == ZYDIS_INSTRUCTION_ENCODING_LEGACY);
b = (instruction.encoding == ZYDIS_INSTRUCTION_ENCODING_LEGACY) ||
(instruction.encoding == ZYDIS_INSTRUCTION_ENCODING_REX2);
break;
case 1:
b = (instruction.encoding == ZYDIS_INSTRUCTION_ENCODING_3DNOW);
Expand Down
20 changes: 18 additions & 2 deletions include/Zydis/Decoder.h
Original file line number Diff line number Diff line change
Expand Up @@ -82,7 +82,12 @@ typedef enum ZydisDecoderMode_
* Enables `KNC` compatibility-mode.
*
* `KNC` and `KNL+` chips are sharing opcodes and encodings for some mask-related instructions.
* Enable this mode to use the old `KNC` specifications (different mnemonics, operands, ..).
* With the EVEX extensions introduced with APX, it's impossible to distinguish between EVEX
* and MVEX at runtime.
*
* Enable this mode to enable KNC support.
*
* WARNING: This will disable decoding of all AVX-512 (EVEX) instructions.
*
* This mode is NOT enabled by default.
*/
Expand Down Expand Up @@ -144,11 +149,22 @@ typedef enum ZydisDecoderMode_
* This mode is enabled by default.
*/
ZYDIS_DECODER_MODE_IPREFETCH,
/**
* Enables the `UD0` compatibility mode.
*
* Some processors decode the `UD0` instruction without a ModR/M byte. Enable this decoder mode
* to mimic this behavior.
*
* This mode is disabled by default.
*/
ZYDIS_DECODER_MODE_UD0_COMPAT,

// TODO: APX mode

/**
* Maximum value of this enum.
*/
ZYDIS_DECODER_MODE_MAX_VALUE = ZYDIS_DECODER_MODE_IPREFETCH,
ZYDIS_DECODER_MODE_MAX_VALUE = ZYDIS_DECODER_MODE_UD0_COMPAT,
/**
* The minimum number of bits required to represent all values of this enum.
*/
Expand Down
178 changes: 164 additions & 14 deletions include/Zydis/DecoderTypes.h
Original file line number Diff line number Diff line change
Expand Up @@ -63,7 +63,7 @@ typedef ZyanU8 ZydisOperandAttributes;
*
* Example: ZMM3 -> [ZMM3..ZMM6]
*/
#define ZYDIS_OATTRIB_IS_MULTISOURCE4 0x01 // (1 << 0)
#define ZYDIS_OATTRIB_IS_MULTISOURCE4 (1 << 0)

/* ---------------------------------------------------------------------------------------------- */
/* Memory type */
Expand Down Expand Up @@ -178,6 +178,10 @@ typedef struct ZydisDecodedOperandImm_
* Signals, if the immediate value is signed.
*/
ZyanBool is_signed;
/**
* Signals, if the immediate value contains an address.
*/
ZyanBool is_address;
/**
* Signals, if the immediate value contains a relative offset. You can use
* `ZydisCalcAbsoluteAddress` to determine the absolute address value.
Expand Down Expand Up @@ -431,11 +435,15 @@ typedef enum ZydisBranchType_
* The instruction is a far (inter-segment) branch instruction.
*/
ZYDIS_BRANCH_TYPE_FAR,
/**
* The instruction is an absolute 64-bit branch instruction.
*/
ZYDIS_BRANCH_TYPE_ABSOLUTE,

/**
* Maximum value of this enum.
*/
ZYDIS_BRANCH_TYPE_MAX_VALUE = ZYDIS_BRANCH_TYPE_FAR,
ZYDIS_BRANCH_TYPE_MAX_VALUE = ZYDIS_BRANCH_TYPE_ABSOLUTE,
/**
* The minimum number of bits required to represent all values of this enum.
*/
Expand Down Expand Up @@ -469,6 +477,7 @@ typedef enum ZydisExceptionClass_
ZYDIS_EXCEPTION_CLASS_AVX8,
ZYDIS_EXCEPTION_CLASS_AVX11,
ZYDIS_EXCEPTION_CLASS_AVX12,
ZYDIS_EXCEPTION_CLASS_AVX14,
ZYDIS_EXCEPTION_CLASS_E1,
ZYDIS_EXCEPTION_CLASS_E1NF,
ZYDIS_EXCEPTION_CLASS_E2,
Expand Down Expand Up @@ -498,11 +507,36 @@ typedef enum ZydisExceptionClass_
ZYDIS_EXCEPTION_CLASS_AMXE4,
ZYDIS_EXCEPTION_CLASS_AMXE5,
ZYDIS_EXCEPTION_CLASS_AMXE6,
ZYDIS_EXCEPTION_CLASS_AMXE1_EVEX,
ZYDIS_EXCEPTION_CLASS_AMXE2_EVEX,
ZYDIS_EXCEPTION_CLASS_AMXE3_EVEX,
ZYDIS_EXCEPTION_CLASS_AMXE4_EVEX,
ZYDIS_EXCEPTION_CLASS_AMXE5_EVEX,
ZYDIS_EXCEPTION_CLASS_AMXE6_EVEX,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_INT,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_KEYLOCKER,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_BMI,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_CCMP,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_CFCMOV,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_CMPCCXADD,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_ENQCMD,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_INVEPT,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_INVPCID,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_INVVPID,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_KMOV,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_PP2,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_SHA,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_CET_WRSS,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_CET_WRUSS,
ZYDIS_EXCEPTION_CLASS_APX_LEGACY_JMPABS,
ZYDIS_EXCEPTION_CLASS_APX_EVEX_RAO_INT,
ZYDIS_EXCEPTION_CLASS_USER_MSR_EVEX,
ZYDIS_EXCEPTION_CLASS_LEGACY_RAO_INT,

/**
* Maximum value of this enum.
*/
ZYDIS_EXCEPTION_CLASS_MAX_VALUE = ZYDIS_EXCEPTION_CLASS_AMXE6,
ZYDIS_EXCEPTION_CLASS_MAX_VALUE = ZYDIS_EXCEPTION_CLASS_LEGACY_RAO_INT,
/**
* The minimum number of bits required to represent all values of this enum.
*/
Expand Down Expand Up @@ -675,6 +709,46 @@ typedef enum ZydisConversionMode_
ZYDIS_CONVERSION_MODE_REQUIRED_BITS = ZYAN_BITS_TO_REPRESENT(ZYDIS_CONVERSION_MODE_MAX_VALUE)
} ZydisConversionMode;

/* ---------------------------------------------------------------------------------------------- */
/* APX source condition code */
/* ---------------------------------------------------------------------------------------------- */

/**
* Defines the `ZydisSourceConditionCode` enum.
*/
typedef enum ZydisSourceConditionCode_
{
ZYDIS_SCC_O = 0,
ZYDIS_SCC_NO = 1,
ZYDIS_SCC_B = 2,
ZYDIS_SCC_NB = 3,
ZYDIS_SCC_Z = 4,
ZYDIS_SCC_NZ = 5,
ZYDIS_SCC_BE = 6,
ZYDIS_SCC_NBE = 7,
ZYDIS_SCC_S = 8,
ZYDIS_SCC_NS = 9,
ZYDIS_SCC_TRUE = 10,
ZYDIS_SCC_FALSE = 11,
ZYDIS_SCC_L = 12,
ZYDIS_SCC_NL = 13,
ZYDIS_SCC_LE = 14,
ZYDIS_SCC_NLE = 15,

/**
* Minimum value of this enum.
*/
ZYDIS_SCC_MIN_VALUE = ZYDIS_SCC_O,
/**
* Maximum value of this enum.
*/
ZYDIS_SCC_MAX_VALUE = ZYDIS_SCC_NLE,
/**
* The minimum number of bits required to represent all values of this enum.
*/
ZYDIS_SCC_REQUIRED_BITS = ZYAN_BITS_TO_REPRESENT(ZYDIS_SCC_MAX_VALUE)
} ZydisSourceConditionCode;

/* ---------------------------------------------------------------------------------------------- */
/* Legacy prefix type */
/* ---------------------------------------------------------------------------------------------- */
Expand Down Expand Up @@ -754,6 +828,54 @@ typedef struct ZydisDecodedInstructionRawRex_
ZyanU8 offset;
} ZydisDecodedInstructionRawRex;

/**
* Detailed info about the `REX2` prefix.
*/
typedef struct ZydisDecodedInstructionRawRex2_
{
/**
* Legacy map 0 (0x0F) selector bit.
*/
ZyanU8 M0;
/**
* Extension of the `ModRM.reg` field (bit 4).
*/
ZyanU8 R4;
/**
* Extension of the `SIB.index` field (bit 4).
*/
ZyanU8 X4;
/**
* Extension of the `ModRM.rm`, `SIB.base`, or `opcode.reg` field (bit 4).
*/
ZyanU8 B4;
/**
* 64-bit operand-size promotion, opcode-extension or PPX hint.
*/
ZyanU8 W;
/**
* Extension of the `ModRM.reg` field (bit 3).
*/
ZyanU8 R3;
/**
* Extension of the `SIB.index` field (bit 3).
*/
ZyanU8 X3;
/**
* Extension of the `ModRM.rm`, `SIB.base`, or `opcode.reg` field (bit 3).
*/
ZyanU8 B3;
/**
* The offset of the effective `REX2` byte, relative to the beginning of the
* instruction, in bytes.
*
* Note that the `REX2` byte can be the first byte of the instruction, which would lead
* to an offset of `0`. Please refer to the instruction attributes to check for the
* presence of the `REX2` prefix.
*/
ZyanU8 offset;
} ZydisDecodedInstructionRawRex2;

/**
* Detailed info about the `XOP` prefix.
*/
Expand Down Expand Up @@ -856,19 +978,23 @@ typedef struct ZydisDecodedInstructionRawEvex
/**
* Extension of the `ModRM.reg` field (inverted).
*/
ZyanU8 R;
ZyanU8 R3;
/**
* Extension of the `SIB.index/vidx` field (inverted).
*/
ZyanU8 X;
ZyanU8 X3;
/**
* Extension of the `ModRM.rm` or `SIB.base` field (inverted).
*/
ZyanU8 B;
ZyanU8 B3;
/**
* High-16 register specifier modifier (inverted).
* High-16 register specifier modifier for the `ModRM.reg` field (inverted).
*/
ZyanU8 R2;
ZyanU8 R4;
/**
* High-16 register specifier modifier for the `ModRM.rm` or `SIB.base` field.
*/
ZyanU8 B4;
/**
* Opcode-map specifier.
*/
Expand All @@ -882,6 +1008,10 @@ typedef struct ZydisDecodedInstructionRawEvex
* (inverted).
*/
ZyanU8 vvvv;
/**
* High-16 register specifier modifier for the `SIB.index/vidx` field (inverted).
*/
ZyanU8 X4;
/**
* Compressed legacy prefix.
*/
Expand All @@ -905,11 +1035,16 @@ typedef struct ZydisDecodedInstructionRawEvex
/**
* High-16 `NDS`/`VIDX` register specifier.
*/
ZyanU8 V2;
ZyanU8 V4;
/**
* Embedded opmask register specifier.
*/
ZyanU8 aaa;

ZyanU8 ND;
ZyanU8 NF;
ZyanU8 SCC;

/**
* The offset of the first evex byte, relative to the beginning of the
* instruction, in bytes.
Expand Down Expand Up @@ -1057,6 +1192,14 @@ typedef struct ZydisDecodedInstructionAvx_
* Signals, if the instruction has a memory-eviction-hint (`KNC` only).
*/
ZyanBool has_eviction_hint;
/**
* The AVX-512 APX source condition code.
*
* The `scc` field contains the actual value of the `EVEX.scc` field and therefore defaults
* to `ZYDIS_SCC_O`. Please check for the `ZYDIS_ATTRIB_HAS_SCC` attribute to determine if
* the instruction actually uses the source condition code.
*/
ZydisSourceConditionCode scc;
// TODO: publish EVEX tuple-type and MVEX functionality
} ZydisDecodedInstructionAvx;

Expand Down Expand Up @@ -1125,6 +1268,7 @@ typedef struct ZydisDecodedInstructionRaw_
union
{
ZydisDecodedInstructionRawRex rex;
ZydisDecodedInstructionRawRex2 rex2;
ZydisDecodedInstructionRawXop xop;
ZydisDecodedInstructionRawVex vex;
ZydisDecodedInstructionRawEvex evex;
Expand Down Expand Up @@ -1206,6 +1350,10 @@ typedef struct ZydisDecodedInstructionRaw_
* Signals, if the immediate value is signed.
*/
ZyanBool is_signed;
/**
* Signals, if the immediate value contains an address.
*/
ZyanBool is_address;
/**
* Signals, if the immediate value contains a relative offset. You can use
* `ZydisCalcAbsoluteAddress` to determine the absolute address value.
Expand Down Expand Up @@ -1359,13 +1507,15 @@ typedef struct ZydisDecoderContext_
struct
{
ZyanU8 W;
ZyanU8 R;
ZyanU8 X;
ZyanU8 B;
ZyanU8 R3;
ZyanU8 R4;
ZyanU8 X3;
ZyanU8 X4;
ZyanU8 B3;
ZyanU8 B4;
ZyanU8 L;
ZyanU8 LL;
ZyanU8 R2;
ZyanU8 V2;
ZyanU8 V4;
ZyanU8 vvvv;
ZyanU8 mask;
} vector_unified;
Expand Down
4 changes: 3 additions & 1 deletion include/Zydis/Generated/EnumISAExt.h
Original file line number Diff line number Diff line change
Expand Up @@ -9,10 +9,11 @@ typedef enum ZydisISAExt_
ZYDIS_ISA_EXT_AMD3DNOW,
ZYDIS_ISA_EXT_AMD3DNOW_PREFETCH,
ZYDIS_ISA_EXT_AMD_INVLPGB,
ZYDIS_ISA_EXT_AMX_BF16,
ZYDIS_ISA_EXT_AMX_FP16,
ZYDIS_ISA_EXT_AMX_INT8,
ZYDIS_ISA_EXT_AMX_TILE,
ZYDIS_ISA_EXT_APXEVEX,
ZYDIS_ISA_EXT_APXLEGACY,
ZYDIS_ISA_EXT_AVX,
ZYDIS_ISA_EXT_AVX2,
ZYDIS_ISA_EXT_AVX2GATHER,
Expand All @@ -33,6 +34,7 @@ typedef enum ZydisISAExt_
ZYDIS_ISA_EXT_CLFSH,
ZYDIS_ISA_EXT_CLWB,
ZYDIS_ISA_EXT_CLZERO,
ZYDIS_ISA_EXT_CMPCCXADD,
ZYDIS_ISA_EXT_ENQCMD,
ZYDIS_ISA_EXT_F16C,
ZYDIS_ISA_EXT_FMA,
Expand Down
Loading
Loading