Upstreaming max597x #3

ASPEED device tree updates for 5.15 - New machines: * TYAN S7106 BMC, a x86 server from about four years ago - Descriptions for the AST2600 ADC, which now has an upstream driver - Lots of GPIO line names. The OpenBMC project has adopted a scheme for naming the lines, and new additions will follow this guide - New I2C devices for Rainier, Everest, EthanolX, Mt Jade - Fixes for fp5280g2 which has seen some recent development, including the addtion of a QEmu machine for testing

ASPEED defconfig updates for 5.16 - Add options that are enabled in the common OpenBMC kernel - Re-enable DRM_FBDEV_EMULATION - Turn on the various sensor drivers that are used in BMC systems, so we can boot test where they are modelled in Qemu

FSI changes for v5.16 - SBEFIFO usersapce interfaces to perform FFDC (First Failure Data Capture) and detect timeouts - A fix to handle multiple messages in flight

ASPEED device tree updates for 5.16, round 2 - New machines: * Inventec Transformers, an x86 family server with an AST2600 BMC - Updates to the Everest and Rainier sensors, gpios and KCS devices - New UART routing device tree description

For Aspeed, HCHalted status depends on not only Run/Stop but also ASS/PSS status. Handshake CMD_RUN on startup instead. OpenBMC-Staging-Count: 2 Signed-off-by: Neal Liu <neal_liu@aspeedtech.com> Acked-by: Alan Stern <stern@rowland.harvard.edu> Reviewed-by: Tao Ren <rentao.bupt@gmail.com> Tested-by: Tao Ren <rentao.bupt@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Fixes: 280a904 ("ehci: fix EHCI host controller initialization sequence") Link: https://lore.kernel.org/r/20210910073619.26095-1-neal_liu@aspeedtech.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add support for the manufacturer ID to the debugfs entries. OpenBMC-Staging-Count: 2 Signed-off-by: Brandon Wyman <bjwyman@gmail.com> Link: https://lore.kernel.org/r/20211004144339.2634330-1-bjwyman@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

There are multiple power supplies that will indicate CFFPS_CCIN_VERSION_1, use the manufacturer ID to determine if it should be treated as version cffps1 or version cffps2. Signed-off-by: Brandon Wyman <bjwyman@gmail.com> Link: https://lore.kernel.org/r/20211004144339.2634330-2-bjwyman@gmail.com [groeck: Fixed continuation line alignment] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add device tree bindings document for the aspeed ast2600 adc device driver. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210831071458.2334-3-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch completes the declare of ADC register bitfields and uses the same prefix ASPEED_ADC_* for these bitfields. In addition, tidy up space alignment of the codes. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210831071458.2334-4-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Keep the model data pointer to driver data for reducing the usage of of_device_get_match_data(). Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-2-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch refactors the model data structure to distinguish the function form different versions of aspeed ADC. - Rename the vref_voltage to vref_fixed_mv and add vref_mv driver data When driver probe will check vref_fixed_mv value and store it to vref_mv which isn't const value. - Add num_channels Make num_channles of iio device can be changed by different model_data - Add need_prescaler flag and scaler_bit_width The need_prescaler flag is used to tell the driver the clock divider needs another Prescaler and the scaler_bit_width to set the clock divider bitfield width. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-3-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add the function to check the vref_fixed_mv and set the value to driver data. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-4-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch uses need_prescaler and scaler_bit_width to set the ADC clock scaler. Reported-by: kernel test robot <lkp@intel.com> Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-5-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch use devm_add_action_or_reset to handle the error in probe phase. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-6-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Make driver to support ast2600 adc device. - Use shared reset controller - Complete the vref configure function - Add the model data for ast2600 adc Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-7-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The ADC clock formula is ast2400/2500: ADC clock period = PCLK * 2 * (ADC0C[31:17] + 1) * (ADC0C[9:0] + 1) ast2600: ADC clock period = PCLK * 2 * (ADC0C[15:0] + 1) They all have one fixed divided 2 and the legacy driver didn't handle it. This patch register the fixed factory clock device as the parent of ADC clock scaler to fix this issue. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-8-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add the function to set the sampling rate and keep the sampling period for a driver used to wait the fresh value. In addition, since the ADC clock is required when initializing the ADC device, move clk_prepare_enable ahead of the initialization phase. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-9-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This patch adds a compensation phase to improve the accuracy of ADC measurement. This is the built-in function through input half of the reference voltage to get the ADC offset. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-10-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

In ast2600, ADC integrate dividing circuit at last input channel for battery sensing. This patch use the dts property "battery-sensing" to enable this feature makes the last channel of each adc can tolerance higher voltage than reference voltage. The offset interface of ch7 will be separated when enabling the battery sensing mode. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-11-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The ADC controller has a trimming register for fine-tune the reference voltage. The trimming value comes from the OTP register which will be written during chip production. This patch will read this OTP value and configure it to the ADC register when the ADC controller probes and using dts property "aspeed,trim-data-valid" to determine whether to execute this flow. Signed-off-by: Billy Tsai <billy_tsai@aspeedtech.com> Link: https://lore.kernel.org/r/20210922081520.30580-12-billy_tsai@aspeedtech.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

There is a spelling mistake in a dev_warn message. Fix it. Signed-off-by: Colin Ian King <colin.king@canonical.com> Link: https://lore.kernel.org/r/20211001120018.17570-1-colin.king@canonical.com Signed-off-by: Jonathan Cameron <Jonathan.Cameron@huawei.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Document the bindings for the Aspeed AST25XX and AST26XX XDMA engine. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Rob Herring <robh@kernel.org> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-2-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

With the exception of the lm5066i, all the devices handled by this driver had been missing their offset ('b') coefficients for direct format readings. Cc: stable@vger.kernel.org Fixes: 58615a9 ("hwmon: (pmbus/lm25066) Add support for LM25056") Fixes: e53e649 ("hwmon: (pmbus/lm25066) Refactor device specific coefficients") Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-2-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

At least as of Revision J, the datasheet has a slightly different value than what we'd had in the driver. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-3-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

Reordering things to put the table before the probe function eliminates the need for it. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-4-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

…066_coeff Maintaining this manually is error prone (there are currently only five chips supported, not six); gcc can do it for us automatically. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Fixes: 666c149 ("hwmon: (pmbus/lm25066) Drop support for LM25063") Link: https://lore.kernel.org/r/20210928092242.30036-5-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

lm25066_coeff is read-only. Mark it as such. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-6-zev@bewilderbeest.net [groeck: Added description] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

The driver doesn't have a struct of_device_id table but supported devices are registered via Device Trees. This is working on the assumption that a I2C device registered via OF will always match a legacy I2C device ID and that the MODALIAS reported will always be of the form i2c:<device>. But this could change in the future so the correct approach is to have an OF device ID table if the devices are registered via OF. Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-7-zev@bewilderbeest.net [groeck: Replaced reference to reasoning with reasoning, fixed checkpatch warnings, fixed compile warning comparing of_id->data w/ i2c_id->driver_data] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

The appropriate mantissa values for the lm25066 family's direct-format current and power readings are a function of the sense resistor employed between the SENSE and VIN pins of the chip. Instead of assuming that resistance is always the same 1mOhm as used in the datasheet, allow it to be configured via a device-tree property ("shunt-resistor-micro-ohms"). Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Link: https://lore.kernel.org/r/20210928092242.30036-8-zev@bewilderbeest.net [groeck: Fixed checkpatch warnings] Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

Signed-off-by: Zev Weiss <zev@bewilderbeest.net> Reviewed-by: Rob Herring <robh@kernel.org> Link: https://lore.kernel.org/r/20210928092242.30036-9-zev@bewilderbeest.net Signed-off-by: Guenter Roeck <linux@roeck-us.net> Signed-off-by: Joel Stanley <joel@jms.id.au>

The XDMA engine embedded in the AST2500 and AST2600 SOCs performs PCI DMA operations between the SOC (acting as a BMC) and a host processor in a server. This commit adds a driver to control the XDMA engine and adds functions to initialize the hardware and memory and start DMA operations. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-3-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

This commits adds a miscdevice to provide a user interface to the XDMA engine. The interface provides the write operation to start DMA operations. The DMA parameters are passed as the data to the write call. The actual data to transfer is NOT passed through write. Note that both directions of DMA operation are accomplished through the write command; BMC to host and host to BMC. The XDMA driver reserves an area of physical memory for DMA operations, as the XDMA engine is restricted to accessing certain physical memory areas on some platforms. This memory forms a pool from which users can allocate pages for their usage with calls to mmap. The space allocated by a client will be the space used in the DMA operation. For an "upstream" (BMC to host) operation, the data in the client's area will be transferred to the host. For a "downstream" (host to BMC) operation, the host data will be placed in the client's memory area. Poll is also provided in order to determine when the DMA operation is complete for non-blocking IO. Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-4-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Users of the XDMA engine need a way to reset it if something goes wrong. Problems on the host side, or user error, such as incorrect host address, may result in the DMA operation never completing and no way to determine what went wrong. Therefore, add an ioctl to reset the engine so that users can recover in this situation. Signed-off-by: Eddie James <eajames@linux.ibm.com> Acked-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/1588697905-23444-5-git-send-email-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

When reading flash contents, try to use the "command mode" if the AHB window configured for the flash module is big enough. Else, just fall back to the "user mode" to perform the read. OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

Implements support for the dual IO read mode on aspeed SMC/FMC controllers which uses both MISO and MOSI lines for data during a read to double the read bandwidth. Still to be done SNOR_PROTO_1_2_2 Based on work from Robert Lippert <roblip@gmail.com> OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

We will need the AHB frequency to set the HCLK settings in the SMC controller to optimize the reads. OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

This is only for SPI controllers as U-Boot should have done it already for the FMC controller using DMAs. The algo is based on the one found in the OpenPOWER pflash tool. It first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find the fastest configuration for the chip. It can be deactivated at boot time with the kernel parameter : aspeed_smc.optimize_read=0 OpenBMC-Staging-Count: 14 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Alexander Soldatov <a.soldatov@yadro.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The optimize read algo can choose a 100MHz SPI frequency which might be a bit too high for dual output IO on some chips, for the W25Q256 on palmetto for instance. The MX66L1G45G on witherspoon should be fine though. Also, the second chip of the FMC controller does not get any optimize settings for reads. Only the first is configured by U-Boot. To fix these two issues, we introduce a "spi-max-frequency" property in the device tree which will be used to cap the optimize read algorithm and we run the algo on the FMC controller chips as well. By default, the frequency setting is 50MHz. OpenBMC-Staging-Count: 13 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

… buffer aspeed_smc_read_from_ahb() only reads the first word which is not what we want. We want to capture a CALIBRATE_BUF_SIZE size window of the flash contents to optimize the read. OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

Switch the default controller value to use the read mode in order to customize the command and use SPINOR_OP_READ_4B (0x13) when the chip supports 4B opcodes. OpenBMC-Staging-Count: 10 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Andrew Jeffery <andrew@aj.id.au>

OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

On the AST2600, we will use it to compute the address of the chip AHB window from the Segment Register value. It also removes the need of aspeed_smc_ahb_base_phy() helper. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

AST2600 will use a different encoding for the addresses defined in the Segment Register. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

The Segment Registers of the AST2600 have a different encoding. A 1MB unit is used and the address range of a flash SPI slave is encoded with offsets in the overall controller window. The previous SoC AST2400 and AST2500 used absolute addresses. Only bits [27:20] are relevant and the end address is an upper bound limit. SPI training yet to come. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

The segments can be disabled on the AST2600 (zero register value). CS0 is open by default but not the other CS. This is closing the access to the flash device in user mode and forbids scanning. For multiple CS, we will need firmware or a DT property to reopen the flash AHB window. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

The read timing compensation register is different on the AST2600 and training will be slightly more complex. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

The AST2600 handles more HCLK divisors than its predecessors. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

The training consists of finding the appropriate read timing delays for the HCLK dividers 2, 3, 4, and 5 and store the results in the Read Timing Compensation register. The previous SoC AST2500 and AST2400 were covering a broader HCLK range [ 1 - 5 ] because the AHB frequency was lower. The algorithm first reads a golden buffer at low speed and then performs reads with different clocks and delay cycles settings to find a breaking point. This selects the default clock frequency for the CEx control register. The current settings are bit optimistic as we pick the first delay giving good results. A safer approach would be to determine an interval and choose the middle value. We might change the approach depending on the results on other systems. Only CS0 is taken into account for the moment. OpenBMC-Staging-Count: 7 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The driver may have overridden the pmbus_read_byte_data() callback, so make sure we use that to achieve expected behaviour. This helps in the MAX31785 case where we may need to perform a one-shot retry of transfers in the face of a failure. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Work around the shonky behaviour seen with the MAX31785 where we fail to set the page register in some circumstances. There's no real elegant way to do this. We can propagate the error up, but that forces us to retry the operation way up the call tree in any number of places. It also forces callers to split out pmbus_set_page() from the pmbus_{read,write}_{byte,word}_data() functions in order to differentiate between a failure to set the page and a failure to read a register (that might not exist, in which case an error is anticiptated). OpenBMC-Staging-Count: 15 Cc: Eddie James <eajames@linux.vnet.ibm.com> Cc: Matt Spinler <mspinler@linux.vnet.ibm.com> Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Eddie James <eajames@linux.vnet.ibm.com> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The MAX31785(A) has shown erratic behaviour across multiple system designs, unexpectedly clock stretching and NAKing transactions. Perform a one-shot retry if necessary for all access attempts. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Tested-by: George Keishing <gkeishin@in.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

For security reasons, some configuration needs to run without /dev/mem but on some occasions, to debug HW for instance, it's still useful to be able to reboot the system with access to physical memory. Add a kernel parameter which activates the /dev/mem device only when 'mem.devmem' is enabled. OpenBMC-Staging-Count: 12 Signed-off-by: Cédric Le Goater <clg@kaod.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

Added device tree binding documentation for Nuvoton BMC NPCM7xx BIOS Post Code (BPC). The NPCM7xx BPC monitoring two configurable I/O addresses written by the host on Low Pin Count (LPC) bus. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add NPCM7xx BIOS post code (BPC) driver, the BPC monitoring two I/O address written by the host on the LPC. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Added device tree binding documentation for Nuvoton BMC NPCM7XX PCI mailbox. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add Nuvoton BMC NPCM7XX PCI Mailbox driver. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> [v5.0: Fix access_ok for API change] Signed-off-by: Joel Stanley <joel@jms.id.au>

Added device tree binding documentation for Nuvoton NPCM7xx Ethernet MAC Controller (EMC). OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add Nuvoton BMC NPCM7xx Ethernet MAC controller (EMC) driver. OpenBMC-Staging-Count: 11 Signed-off-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Most of our machines don't have PHYs between the NIC and the BMC over their NC-SI port. We don't want to use the kernel NC-SI machinery, but we do want phyless support. OpenBMC-Staging-Count: 3 Signed-off-by: William A. Kennington III <wak@google.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210327004920.388957-1-wak@google.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Witherspoon contains four dual-tach fans. We configure them go to 100% when the fault pin is asserted, and disable the fan ramp watchdog. This preserves the behaviour of the previous driver. OpenBMC-Staging-Count: 15 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Joel Stanley <joel@jms.id.au>

FIU, ADC, RST, VCD and SPI, PECI, regulator and HGPIO pins nodes. OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This is the remaining non-mainline component of the patch that adds the NPCM730 common device tree. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This is the remaining non-mainline component of the patch that adds the GSJ machine. OpenBMC-Staging-Count: 4 Signed-off-by: Fran Hsu <Fran.Hsu@quantatw.com> Reviewed-by: Benjamin Fair <benjaminfair@google.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

This is the remaining non-mainline component of the patch that adds the Opympus machine. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

These modules need a phandle reference to the fuse device in order to read out system specific settings. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210119223412.223492-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add device tree documentation for Nuvoton BMC ECC OpenBMC-Staging-Count: 9 Signed-off-by: George Hung <george.hung@quantatw.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add support for the Nuvoton NPCM7xx SoC EDAC driver NPCM7xx ECC datasheet from nuvoton.israel-Poleg: "Cadence DDR Controller User’s Manual For DDR3 & DDR4 Memories" Tested: Forcing an ECC error event Write a value to the xor_check_bits parameter that will trigger an ECC event once that word is read For example, to force a single-bit correctable error on bit 0 of the user-word space shown, write 0x75 into that byte of the xor_check_bits parameter and then assert fwc (force write check) bit to 'b1' (mem base: 0xf0824000, xor_check_bits reg addr: 0x178) $ devmem 0xf0824178 32 0x7501 To force a double-bit un-correctable error for the user-word space, write 0x03 into that byte of the xor_check_bits parameter $ devmem 0xf0824178 32 0x301 OpenBMC-Staging-Count: 9 Signed-off-by: George Hung <george.hung@quantatw.com> Reviewed-by: Avi Fishman <avifishman70@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The AST2600 SoC contains the same IPMI (BT/KCS) devices as the AST2500. OpenBMC-Staging-Count: 7 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

The AST2600 SoC contains the same LPC register set as the AST2500. OpenBMC-Staging-Count: 7 Reviewed-by: Andrew Jeffery <andrew@aj.id.au> Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

BCLK for PCI/PCIe bus should be enabled always with having the CLK_IS_CRITICAL flag otherwise it will be disabled at kernel late initcall phase as an unused clock, and eventually it causes unexpected behavior on BMC features that are connected to the host through PCI/PCIe bus. OpenBMC-Staging-Count: 6 Signed-off-by: Jae Hyun Yoo <jae.hyun.yoo@linux.intel.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

Make use of spi_max_transfer_size to avoid requesting transfers that are too large for some spi controllers. Signed-off-by: Brad Bishop <bradleyb@fuzziesquirrel.com> Signed-off-by: Eddie James <eajames@linux.ibm.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200820170228.42053-8-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Document the bindings for the IBM Operation Panel, which provides a simple interface to control a server. It has a display and three buttons. Also update MAINTAINERS for the new file. OpenBMC-Staging-Count: 4 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Rob Herring <robh@kernel.org> Acked-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200909203059.23427-2-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add a driver to get the button events from the panel and provide them to userspace with the input subsystem. The panel is connected with I2C and controls the bus, so the driver registers as an I2C slave device. OpenBMC-Staging-Count: 4 Signed-off-by: Eddie James <eajames@linux.ibm.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20200909203059.23427-3-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

We must ensure the tx descriptor updates are visible before updating the tx pointer. This resolves the tx hangs observed on the 2600 when running iperf: root@ast2600:~# iperf3 -c 192.168.86.146 -R Connecting to host 192.168.86.146, port 5201 Reverse mode, remote host 192.168.86.146 is sending [ 5] local 192.168.86.173 port 43886 connected to 192.168.86.146 port 5201 [ ID] Interval Transfer Bitrate [ 5] 0.00-1.00 sec 90.7 MBytes 760 Mbits/sec [ 5] 1.00-2.00 sec 91.7 MBytes 769 Mbits/sec [ 5] 2.00-3.00 sec 91.7 MBytes 770 Mbits/sec [ 5] 3.00-4.00 sec 91.7 MBytes 769 Mbits/sec [ 5] 4.00-5.00 sec 91.8 MBytes 771 Mbits/sec [ 5] 5.00-6.00 sec 91.8 MBytes 771 Mbits/sec [ 5] 6.00-7.00 sec 91.9 MBytes 771 Mbits/sec [ 5] 7.00-8.00 sec 91.4 MBytes 767 Mbits/sec [ 5] 8.00-9.00 sec 91.3 MBytes 766 Mbits/sec [ 5] 9.00-10.00 sec 91.9 MBytes 771 Mbits/sec [ 5] 10.00-11.00 sec 91.8 MBytes 770 Mbits/sec [ 5] 11.00-12.00 sec 91.8 MBytes 770 Mbits/sec [ 5] 12.00-13.00 sec 90.6 MBytes 761 Mbits/sec [ 5] 13.00-14.00 sec 45.2 KBytes 370 Kbits/sec [ 5] 14.00-15.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 15.00-16.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 16.00-17.00 sec 0.00 Bytes 0.00 bits/sec [ 5] 17.00-18.00 sec 0.00 Bytes 0.00 bits/sec [ 67.031671] ------------[ cut here ]------------ [ 67.036870] WARNING: CPU: 1 PID: 0 at net/sched/sch_generic.c:442 dev_watchdog+0x2dc/0x300 [ 67.046123] NETDEV WATCHDOG: eth2 (ftgmac100): transmit queue 0 timed out OpenBMC-Staging-Count: 4 Fixes: 52c0cae ("ftgmac100: Remove tx descriptor accessors") Link: https://lore.kernel.org/r/20201020220639.130696-1-joel@jms.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>

Add read only flag to all divider clocks except SPI3 clock. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-2-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add calibration to improve accuracy measurement when using internal reference voltage. Tthe calibration values taken are from the FUSE module. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-4-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add device tree restart priority and three reset types support. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-7-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Reviewed-by: Joel Stanley <joel@jms.id.au> Link: https://lore.kernel.org/r/20210113200010.71845-8-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Add generic pin persist configuration support. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-9-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-10-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Modify the IRQ handler in the NPCM PSPI driver to support SPI full duplex communication. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-11-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Added device tree binding documentation for Nuvoton NPCM7XX JTAG master. OpenBMC-Staging-Count: 4 Signed-off-by: Stanley Chu <yschu@nuvoton.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-12-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

The NPCM7xx JTAG master using GPIO lines and NPCM PSPI bus. OpenBMC-Staging-Count: 4 Signed-off-by: Stanley Chu <yschu@nuvoton.com> Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210113200010.71845-13-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

Once the syscon phandle is not found the WD reset status will not be supported, so return to the function caller. OpenBMC-Staging-Count: 4 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Link: https://lore.kernel.org/r/20210119223412.223492-5-tmaimon77@gmail.com Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 11 Signed-off-by: Tomer Maimon <tmaimon77@gmail.com> Signed-off-by: Joel Stanley <joel@jms.id.au>

witherspoon hardware and p9 chips have very sensitive requirements for the cfam-reset. We're seeing power faults with the kernel based cfam reset due to this. Could adapt the power application to use the new kernel based cfam reset interface but there's not a lot to be gained there since the power application is going away with p10 and this limitation is not present in p10. OpenBMC-Staging-Count: 3 Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20210308225419.46530-17-eajames@linux.ibm.com Signed-off-by: Joel Stanley <joel@jms.id.au>

The existing IPMI chardev encodes IPMI behaviours as the name suggests. However, KCS devices are useful beyond IPMI (or keyboards), as they provide a means to generate IRQs and exchange arbitrary data between a BMC and its host system. Implement a "raw" KCS character device that exposes the IDR, ODR and STR registers to userspace via read() and write() implemented on a character device: +--------+--------+---------+ | Offset | read() | write() | +--------+--------+---------+ | 0 | IDR | ODR | +--------+--------+---------+ | 1 | STR | STR | +--------+--------+---------+ This interface allows userspace to implement arbitrary (though somewhat inefficient) protocols for exchanging information between a BMC and host firmware. Conceptually the KCS interface can be used as an out-of-band mechanism for interrupt-signaled control messages while bulk data transfers occur over more appropriate interfaces between the BMC and the host (which may lack their own interrupt mechanism, e.g. LPC FW cycles). poll() is provided, which will wait for IBF or OBE conditions for data reads and writes respectively. Reads of STR on its own never blocks, though accessing both offsets in the one system call may block if the data registers are not ready. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210623033854.587464-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>

OpenBMC-Staging-Count: 3 Signed-off-by: Joel Stanley <joel@jms.id.au>

Make the Tacoma KCS nodes reflect the configuration of the Rainier and Everest nodes. OpenBMC-Staging-Count: 3 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Link: https://lore.kernel.org/r/20210709151119.2683600-1-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>

Enable sensors and other drivers used by OpenBMC systems. Turn on some options to help debugging and testing. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au>

The devicetree binding allows specifying which pins are GPIO vs LED. Limiting the instantiated gpiochip to just these pins as the driver currently does requires an arbitrary mapping between pins and GPIOs, but such a mapping is not implemented by the driver. As a result, specifying GPIOs in such a way that they don't map 1-to-1 to pin indexes does not function as expected. Establishing such a mapping is more complex than not and even if we did, doing so leads to a slightly hairy userspace experience as the behaviour of the PCA955x gpiochip would depend on how the pins are assigned in the devicetree. Instead, always expose all pins via the gpiochip to provide a stable interface and track which pins are in use. Specifying a pin as `type = <PCA955X_TYPE_GPIO>;` in the devicetree becomes a no-op. I've assessed the impact of this change by looking through all of the affected devicetrees as of the tag leds-5.15-rc1: ``` $ git grep -l 'pca955[0123]' $(find . -name dts -type d) arch/arm/boot/dts/aspeed-bmc-ibm-everest.dts arch/arm/boot/dts/aspeed-bmc-ibm-rainier.dts arch/arm/boot/dts/aspeed-bmc-opp-mihawk.dts arch/arm/boot/dts/aspeed-bmc-opp-mowgli.dts arch/arm/boot/dts/aspeed-bmc-opp-swift.dts arch/arm/boot/dts/aspeed-bmc-opp-tacoma.dts arch/arm/boot/dts/aspeed-bmc-opp-witherspoon.dts ``` These are all IBM-associated platforms. I've analysed both the devicetrees and schematics where necessary to determine whether any systems hit the hazard of the current broken behaviour. For the most part, the systems specify the pins as either all LEDs or all GPIOs, or at least do so in a way such that the broken behaviour isn't exposed. The main counter-point to this observation is the Everest system whose devicetree describes a large number of PCA955x devices and in some cases has pin assignments that hit the hazard. However, there does not seem to be any use of the affected GPIOs in the userspace associated with Everest. Regardless, any use of the hazardous GPIOs in Everest is already broken, so let's fix the interface and then fix any already broken userspace with it. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210921043936.468001-2-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>

It's valid to use the PCA955x devices just for GPIOs and not for LEDs. In this case, as PCA955X_TYPE_GPIO is now equivalent to PCA955X_TYPE_NONE, remove the test for whether we have any child nodes specified in the devicetree. A consequence of this is it's now possible to bind the driver to a PCA955x device when dynamically instantiated through the I2C subsystem's `new_device` interface. OpenBMC-Staging-Count: 2 Signed-off-by: Andrew Jeffery <andrew@aj.id.au> Reviewed-by: Joel Stanley <joel@jms.id.au> Reviewed-by: Linus Walleij <linus.walleij@linaro.org> Reviewed-by: Andy Shevchenko <andy.shevchenko@gmail.com> Link: https://lore.kernel.org/r/20210921043936.468001-3-andrew@aj.id.au Signed-off-by: Joel Stanley <joel@jms.id.au>

Split the primary and secondary BIOS SPI EEPROMs in 2 partitions OpenBMC-Staging-Count: 2 Signed-off-by: George Hung <george.hung@quantatw.com> Link: https://lore.kernel.org/r/20211008053006.31961-1-george.hung@quantatw.com

This driver was originally written to use the regmap abstraction with no clear benefit. As the registers are always mmio and there is no sharing of the region with other devices, we can safely read and write without the locking that regmap provides. This reduces the code size of the driver by about 25%. OpenBMC-Staging-Count: 2 Signed-off-by: Joel Stanley <joel@jms.id.au> Message-Id: <20210903051039.307991-1-joel@jms.id.au> Signed-off-by: Corey Minyard <cminyard@mvista.com>

Print the SPI engine status register when an error is detected. This will aid tremendously in debugging failed transactions. OpenBMC-Staging-Count: 2 Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211004195149.29759-1-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

Change the name of the partitions for BIOS primary and secondary SPI EEPROMs. OpenBMC-Staging-Count: 2 Signed-off-by: George Hung <george.hung@quantatw.com> Link: https://lore.kernel.org/r/20211026054904.8888-1-george.hung@quantatw.com Signed-off-by: Joel Stanley <joel@jms.id.au>

There was nothing to protect multiple SPI controllers on the same FSI2SPI device from being accessed through the FSI2SPI device at the same time. For example, multiple writes to the command and data registers might occur for different SPI controllers, resulting in complete chaos in the SPI engine. To prevent this, add a FSI2SPI device level mutex and lock it in the SPI register read and write functions. OpenBMC-Staging-Count: 1 Fixes: bbb6b2f ("spi: Add FSI-attached SPI controller driver") Signed-off-by: Eddie James <eajames@linux.ibm.com> Link: https://lore.kernel.org/r/20211026193327.52420-1-eajames@linux.ibm.com Signed-off-by: Mark Brown <broonie@kernel.org> Signed-off-by: Joel Stanley <joel@jms.id.au>

Add driver support for the UART routing control. Users can perform runtime configuration of the RX muxes among the UART controllers and the UART IO pins. The sysfs interface is also exported for the convenience of routing paths check and update. Signed-off-by: Oskar Senft <osk@google.com> Signed-off-by: Chia-Wei Wang <chiawei_wang@aspeedtech.com> Signed-off-by: Joel Stanley <joel@jms.id.au> Tested-by: Lei YU <yulei.sh@bytedance.com> Link: https://lore.kernel.org/r/20210927023053.6728-5-chiawei_wang@aspeedtech.com Link: https://lore.kernel.org/r/20211022000616.481772-1-joel@jms.id.au' Signed-off-by: Arnd Bergmann <arnd@arndb.de>

The MAX597x is a smart switch with fault protection and sensor readings. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>

Implement a regulator driver with IRQ support for fault management. Written against documentation [1] and [2] and tested on real hardware. The MAX597x cannot regulate the output voltage and thus acts as switch with seperate voltage and current monitors. Every channel has it's own regulator supply nammed 'vss1-supply' and 'vss2-supply'. The driver requires the 'shunt-resistor-micro-ohms' to be present in the devicetree to properly calculate current related values. You must specify compatible devictree layout: regulator@3a { reg = <0x3a>; vss1-supply = <&p3v3>; compatible = "maxim,max5978"; ... regulators { sw0_ref: SW0 { regulator-compatible = "SW0"; shunt-resistor-micro-ohms = <12000>; ... } } } 1: https://datasheets.maximintegrated.com/en/ds/MAX5970.pdf 2: https://datasheets.maximintegrated.com/en/ds/MAX5978.pdf Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>

The MAX597x monitors voltages and current for fault protection. Allow to read the measured values using the IIO framework. On MAX5978 two IIO channels are exposed and on MAX5970 4 IIO channels are exposed. Signed-off-by: Patrick Rudolph <patrick.rudolph@9elements.com> Signed-off-by: Marcello Sylvester Bauer <sylv@sylv.io>

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