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errata(pcie): Change of rule from SBSA to BSA #166

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Merged
chetan-rathore merged 1 commit into from
Nov 27, 2025
Merged

errata(pcie): Change of rule from SBSA to BSA #166

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4 changes: 4 additions & 0 deletions docs/bsa/arm_bsa_testcase_checklist.rst
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Expand Up @@ -219,6 +219,8 @@ The below table provides the following details
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|845 |PCIe Device Memory mapping support |L1 |PCI_MM_01 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|891 |Steering Tag value properties |FR |B_PCIe_11 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|894 |PCIe Normal Memory mapping support |L1 |PCI_MM_03 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|895 |PCIe & PE common physical memory view |L1 |PCI_MM_05 |Yes |Yes |Yes |Yes# |Yes |Yes |No |
Expand Down Expand Up @@ -253,6 +255,8 @@ The below table provides the following details
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|1517 |Check BME functionality of RP |L1 |PCI_IN_05 |No |No |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|1530 |Enable and disable STE.DCP bit |FR |B_PCIe_10 |No |No |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|1533 |MSI(-X) triggers intr with unique ID |L1 |PCI_MSI_2 |No |No |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+------------------------------------------------------------+-----+-----+-----+-----+----------+-----+-------------------+
|1535 |MSI-cap device can target any ITS blk |L1 |ITS_04 |No |No |No |Yes |Yes |No |Yes |
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4 changes: 0 additions & 4 deletions docs/sbsa/arm_sbsa_testcase_checklist.rst
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Expand Up @@ -271,8 +271,6 @@ The below table provides the following details
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|890 |Check RP Extensions for DPC |FR |PCI_ER_09 |Yes |Yes |Yes |No |No |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|891 |Steering Tag value properties |FR |S_PCIe_11 |Yes |Yes#|Yes |Yes |No |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|892 |Secondary PCIe ECap Check: iEP Pair |L6 |IE_REG_6 |Yes |Yes |Yes |Yes |No |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|893 |Switches must support ACS if P2P |FR |GPU_03 |Yes |Yes |Yes |Yes |No |
Expand Down Expand Up @@ -313,8 +311,6 @@ The below table provides the following details
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|1529 |RAS ERR record for external abort |FR |PCI_ER_07 |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|1530 |Enable and disable STE.DCP bit |FR |S_PCIe_10 |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|1531 |Arrival order & Gathering Check: iEP |L6 |IE_ORD_1 |No |Yes |Yes |No |Yes |
+-------+--------------------------------------------+-----+----------------------------------------------------+----------------+----+----------+-----+-------------------+
|1532 |Check ordered writes flush prev writes |FR |S_PCIe_08 |No |Yes |Yes |No |Yes |
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1 change: 1 addition & 0 deletions test_pool/Makefile
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Expand Up @@ -28,6 +28,7 @@ ifeq ($(ACS), bsa)
obj-m += bsa_acs_test.o
bsa_acs_test-objs += $(TEST_POOL)/pcie/p001.o \
$(TEST_POOL)/pcie/p045.o \
$(TEST_POOL)/pcie/p091.o \
$(TEST_POOL)/pcie/p094.o \
$(TEST_POOL)/pcie/p095.o \
$(TEST_POOL)/pcie/p096.o \
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2 changes: 1 addition & 1 deletion test_pool/exerciser/e030.c
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Expand Up @@ -28,7 +28,7 @@

#define TEST_NUM (ACS_EXERCISER_TEST_NUM_BASE + 30)
#define TEST_DESC "Enable and disable STE.DCP bit "
#define TEST_RULE "S_PCIe_10"
#define TEST_RULE "B_PCIe_10"

#define TEST_DATA_NUM_PAGES 4

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2 changes: 1 addition & 1 deletion test_pool/pcie/p091.c
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Expand Up @@ -21,7 +21,7 @@
#include "val/include/val_interface.h"

#define TEST_NUM (ACS_PCIE_TEST_NUM_BASE + 91)
#define TEST_RULE "S_PCIe_11"
#define TEST_RULE "B_PCIe_11"
#define TEST_DESC "Steering Tag value properties "

static
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2 changes: 2 additions & 0 deletions tools/cmake/infra/bsa_test.txt
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Expand Up @@ -95,6 +95,7 @@ p038.c
p039.c
p042.c
p045.c
p091.c
p094.c
p095.c
p096.c
Expand All @@ -114,6 +115,7 @@ e014.c
e015.c
e016.c
e017.c
e030.c
e033.c
e035.c
e039.c
Expand Down
2 changes: 0 additions & 2 deletions tools/cmake/infra/sbsa_test.txt
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Expand Up @@ -109,7 +109,6 @@ p087.c
p088.c
p089.c
p090.c
p091.c
p092.c
p093.c
p094.c
Expand All @@ -128,7 +127,6 @@ e026.c
e027.c
e028.c
e029.c
e030.c
e036.c
pmu001.c
pmu002.c
Expand Down
2 changes: 0 additions & 2 deletions val/include/rule_based_execution_enum.h
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Expand Up @@ -496,8 +496,6 @@ typedef enum {
S_PCIe_09,
S_PCIe_07,
S_PCIe_08,
S_PCIe_10,
S_PCIe_11,
S_L8CXL_1,
S_L3GI_02, /* GIC rule is in part of PCIe module */

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10 changes: 10 additions & 0 deletions val/src/bsa_execute_test.c
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Expand Up @@ -538,6 +538,12 @@ val_bsa_pcie_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
#endif
}

#if defined(TARGET_LINUX) || defined(TARGET_BAREMETAL)
if (g_bsa_level > 1 || g_bsa_only_level == 2) {
status |= p091_entry(num_pe);
}
#endif

}

view_print_info(MODULE_END);
Expand Down Expand Up @@ -893,6 +899,10 @@ val_bsa_exerciser_execute_tests(uint32_t num_pe, uint32_t *g_sw_view)
status |= e033_entry(num_pe);
status |= e039_entry(num_pe);
}

if (g_bsa_level > 1 || g_bsa_only_level == 2) {
status |= e030_entry(num_pe);
}
}

val_smmu_stop();
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2 changes: 0 additions & 2 deletions val/src/rule_enum_string_map.c
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Expand Up @@ -449,8 +449,6 @@ char *rule_id_string[RULE_ID_SENTINEL] = {
[S_PCIe_09] = "S_PCIe_09",
[S_PCIe_07] = "S_PCIe_07",
[S_PCIe_08] = "S_PCIe_08",
[S_PCIe_10] = "S_PCIe_10",
[S_PCIe_11] = "S_PCIe_11",
[S_L4PCI_1] = "S_L4PCI_1",
[S_L4PCI_2] = "S_L4PCI_2",
[S_L6PCI_1] = "S_L6PCI_1",
Expand Down
2 changes: 0 additions & 2 deletions val/src/rule_lookup.c
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Expand Up @@ -196,8 +196,6 @@ const sbsa_rule_entry_t sbsa_rule_list[] = {
{ S_PCIe_06, SBSA_LEVEL_FR },
{ S_PCIe_07, SBSA_LEVEL_FR },
{ S_PCIe_08, SBSA_LEVEL_FR },
{ S_PCIe_10, SBSA_LEVEL_FR },
{ S_PCIe_11, SBSA_LEVEL_FR },
{ PCI_ER_07, SBSA_LEVEL_FR },
{ PCI_ER_08, SBSA_LEVEL_FR },
{ PCI_ER_09, SBSA_LEVEL_FR },
Expand Down
6 changes: 3 additions & 3 deletions val/src/rule_metadata.c
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Expand Up @@ -2181,15 +2181,15 @@ rule_test_map_t rule_test_map[RULE_ID_SENTINEL] = {
.flag = BASE_RULE,
.test_num = ACS_PE_TEST_NUM_BASE + 32,
},
[S_PCIe_10] = {
[B_PCIe_10] = {
.test_entry_id = E030_ENTRY,
.module_id = PCIE,
.rule_desc = "Enable and disable STE.DCP bit",
.platform_bitmask = PLATFORM_BAREMETAL | PLATFORM_UEFI,
.flag = BASE_RULE,
.test_num = ACS_EXERCISER_TEST_NUM_BASE + 30,
},
[S_PCIe_11] = {
[B_PCIe_11] = {
.test_entry_id = P091_ENTRY,
.module_id = PCIE,
.rule_desc = "Steering Tag value properties",
Expand Down Expand Up @@ -2511,6 +2511,7 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
#if defined(TARGET_LINUX)
[P001_ENTRY] = p001_entry,
[P045_ENTRY] = p045_entry, // used in wrapper.
[P091_ENTRY] = p091_entry, // used in wrapper.
[P103_ENTRY] = p103_entry, // used in wrapper.
[P094_ENTRY] = p094_entry, // used in wrapper.
[P104_ENTRY] = p104_entry, // used in wrapper.
Expand All @@ -2529,7 +2530,6 @@ test_entry_fn_t test_entry_func_table[TEST_ENTRY_SENTINEL] = {
[M007_ENTRY] = m007_entry,
/* Skip build of sbsa only tests for BSA */
#ifndef BSA_LINUX_BUILD
[P091_ENTRY] = p091_entry,
[I023_ENTRY] = i023_entry,
[P046_ENTRY] = p046_entry,
#endif /* BSA_LINUX_BUILD */
Expand Down
6 changes: 0 additions & 6 deletions val/src/sbsa_execute_test.c
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Expand Up @@ -370,11 +370,6 @@ val_sbsa_pcie_execute_tests(uint32_t level, uint32_t num_pe)

#endif

#if defined(TARGET_LINUX) || defined(TARGET_BAREMETAL)
if (((level > 7) && (g_sbsa_only_level == 0)) || (g_sbsa_only_level == 8))
status |= p091_entry(num_pe);
#endif

if (((level > 5) && (g_sbsa_only_level == 0)) || (g_sbsa_only_level == 6)) {
#if defined(TARGET_LINUX) || defined(TARGET_BAREMETAL)
status |= p103_entry(num_pe);
Expand Down Expand Up @@ -688,7 +683,6 @@ val_sbsa_exerciser_execute_tests(uint32_t level, uint32_t num_pe)
status |= e027_entry(num_pe);
status |= e028_entry(num_pe);
status |= e029_entry(num_pe);
status |= e030_entry(num_pe);
status |= e032_entry(num_pe);
}

Expand Down