Merge pull request #10156 from juhoeskeli/MTB_STM_L475_uart_clock_fix

MTB_STM_L475: fix UART clock

targets/TARGET_STM/TARGET_STM32L4/TARGET_STM32L475xG/TARGET_MTB_STM_L475/system_clock.c

@@ -171,11 +171,12 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
  HAL_RCC_ClockConfig(&RCC_ClkInitStruct, FLASH_LATENCY_0);
 
  // Enable HSE oscillator and activate PLL with HSE as source
- RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_HSI;
+ RCC_OscInitStruct.OscillatorType = RCC_OSCILLATORTYPE_HSE | RCC_OSCILLATORTYPE_LSE | RCC_OSCILLATORTYPE_HSI;
  if (bypass == 0) {
- RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ RCC_OscInitStruct.HSEState = RCC_HSE_ON; // External 8 MHz xtal on OSC_IN/OSC_OUT
+ RCC_OscInitStruct.LSEState = RCC_LSE_ON;
  } else {
- RCC_OscInitStruct.HSEState  = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
+ RCC_OscInitStruct.HSEState = RCC_HSE_BYPASS; // External 8 MHz clock on OSC_IN
  }
  RCC_OscInitStruct.HSIState = RCC_HSI_OFF;
  RCC_OscInitStruct.PLL.PLLSource = RCC_PLLSOURCE_HSE; // 8 MHz
@@ -200,15 +201,10 @@ uint8_t SetSysClock_PLL_HSE(uint8_t bypass)
  return 0; // FAIL
  }
 
- RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_USB;
- RCC_PeriphClkInit.UsbClockSelection = RCC_USBCLKSOURCE_PLLSAI1;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Source = RCC_PLLSOURCE_HSE;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1M = 1;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1N = 12;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1P = RCC_PLLP_DIV7;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1Q = RCC_PLLQ_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1R = RCC_PLLR_DIV2;
- RCC_PeriphClkInit.PLLSAI1.PLLSAI1ClockOut = RCC_PLLSAI1_48M2CLK;
+ // Select LSE output as LPUART1 clock source
+ RCC_PeriphClkInit.PeriphClockSelection = RCC_PERIPHCLK_RTC | RCC_PERIPHCLK_LPUART1;
+ RCC_PeriphClkInit.Lpuart1ClockSelection = RCC_LPUART1CLKSOURCE_LSE;
+ RCC_PeriphClkInit.RTCClockSelection = RCC_RTCCLKSOURCE_LSE;
  if (HAL_RCCEx_PeriphCLKConfig(&RCC_PeriphClkInit) != HAL_OK) {
  return 0; // FAIL
  }