-
Notifications
You must be signed in to change notification settings - Fork 3k
Release candidate for mbed-os-5.7.2 #5767
New issue
Have a question about this project? Sign up for a free GitHub account to open an issue and contact its maintainers and the community.
By clicking “Sign up for GitHub”, you agree to our terms of service and privacy statement. We’ll occasionally send you account related emails.
Already on GitHub? Sign in to your account
Conversation
ea66503
to
7d2675c
Compare
/morph build |
/morph mbed2-release |
Result: FAILUREYour command has finished executing! Here's what you wrote!
|
One of the node was down, I started the service it should be fine now. /morph mbed2-release |
Build : SUCCESSBuild number : 771 Triggering tests/morph test |
Result: FAILUREYour command has finished executing! Here's what you wrote!
OutputBuild failed! |
@bulislaw
This is a blocker for 5.7.2 please investigate asap! |
Exporter Build : SUCCESSBuild number : 425 |
Test : SUCCESSBuild number : 607 |
@adbridge A quick fix would be to outright disable the export of the target in targets.json by blanking out the release_versions array for both A9 targets. As for the actual issue, it looks like the file is relying on device-specific information, which seems backwards to what files in the cmsis directory should be doing. |
This change comes from: At the moment we do not have RTE component, neither CMSIS_device_header set up, thus cmsis.h used there instead. The file is actually there: https://github.com/ARMmbed/mbed-os/blob/master/targets/TARGET_RENESAS/TARGET_RZ_A1H/device/cmsis.h. I am more wondering why Update: build tools have cmsis path, no target path involved, this is why it fails |
#5770 should fix the issue |
Pending official update from STM, add memory barriers to the Ethernet HAL code for the STM32F7xx family. Cortex-M7 has a merging write buffer that is not automatically flushed by accesses to devices, so without these DMBs, we sometimes lose synch with the transmitter. The DMBs are architecturally needed in every version of this HAL, but adding just to the STM32F7 version for now to clear test, as the problem has only been observed on Cortex-M7-based devices. Fixes #5622.
The K64F Ethernet driver installs an interrupt handler that sets thread flags, and this could be called before the thread was initialised, so it would use a NULL thread ID. This triggers an RTX error-checking trap in debug builds, and could also lead to other problems with received packets not being processed. Adjusted so the RX interrupt handler does nothing if the thread isn't initialised yet, and manually trigger a RX event flag after initialising the thread in case any interrupts were ignored. An alternative would have been to implement eth_arch_enable_interrupts, but this mechanism is not present in the EMAC world - drivers will have to start returning interrupts in their power up. Fixes #5680
When specifying a full channel mask in .lib and setting the channel to zero, device does proper channel scan. For Thread, channel must be specified for router. Sleepy devices don't respect the channel settings but do a full channel scan at the start. + Modified the channel mask print to use hex.
- ADuCM3029 is the MCU name for EV_COG_AD3029LZ - ADuCM4050 is the MCU name for EV_COG_AD4050LZ
For supporting tp CMSIS5/RTX5, I changed the start-up processing of 3 toolchains(ARMCC, GCC_ARM, IAR) and updated the register definition of PEACH specific. In addition, I changed the linker script files to implement the dynamic HEAP the same as Cortex-M targets.Since GR-PEACH's HEAP was a fixed area, I changed the label name(ZI_DATA to RW_IRAM1) and replaced the allocation of STACK/HEAP.
By updating to the codes of CMSIS5/RTX5, GIC_SetConfigration() function was added for Cortex-A, this function is set the interrupt configuration using GIC's ICFGR register. Therefore, I added this function to satisfy Cortex-A interrupt spec in the below files. "can_api.c", "ethernet_api.c", "gpio_irq_api.c", "i2c_api.c", "spi_api.c" and "us_ticker.c"
I added the below definitions for working "Dynamic Stack" and "Dynamic heap" on Mbed OS by referencing with the codes of Cortex-M target board. "ISR_STACK_START", "ISR_STACK_SIZE", "INITIAL_SP", "HEAP_START" and "HEAP_SIZE"
I changed disable_irq() / enable_irq() to core_util_critical_section_enter() / core_util_critical_section_exit() by utilizing "mbed_critical" function in the below drivers. - serial_api.c - us_ticker.c
Although the extened RTC is supported by #5363 commit ("Add support and tests for extended RTC"), it seems that the changes was overlooked in RZ_A1H_api.c. So I added the changes with reference to other rtc_api.c.
I changed the python and json files to re-registering GR-PEACH to Mbed OS 5.
I added the definition of "Cortex-A9" for core support of ARMCC and ARMC6 in arm.py.
I modified "space" character from 2-byte code to 1-byte code in "heap and stack" test main.
"malloc" test is used a simple thread that executes only malloc and free, but it seems that there is a difference in the stack used between Cortex-A and Cortex-M. As a result of check, in Cortex-A, program aborts because of the lack of stack when THREAD_STACK_SIZE is 256, workes properly when THREAD_STACK_SIZE is 512 at least. Since it seems that the definition processing of "DEFAULT_STACK_SIZE" was gone from Mbed OS by updating CMSIS5/RTX5, I setted 512 directly for Cortex-A.
Impossible to make USBHost working on this board. Remove it for now until a fix is found.
Most of our IP stacks don't allow removal of interfaces so interface destructor can not reliably clean up. Therefore we cannot rely its behaviours in test case. Instead run interface->disconnect() in case interface was already created.
As this is os tick implementation for rtos, it should not be compilied if rtos not present (mbed 2)
Travis: dsp only for cortex-m
Build api used to build cmsis separately (how mbed 2 is being build). This is currently not how cmsis is being defined. As there target dependencies in some cases, we should include paths from targets when building cmsis
Use mbed critical section
As it does not share the codebase with RZ A1H, it needs to be disabled until bring it up to date with the latest changes to cmsis. There are changes regarding caches, mmu and others
7d2675c
to
37641d7
Compare
/morph mbed2-release |
/morph build |
Result: FAILUREYour command has finished executing! Here's what you wrote!
OutputBuild failed! |
Build : FAILUREBuild number : 776 |
This reverts commit 1bb2ca6.
/morph mbed2-release |
/morph build |
Result: SUCCESSYour command has finished executing! Here's what you wrote!
|
Build : SUCCESSBuild number : 777 Triggering tests/morph test |
Exporter Build : FAILUREBuild number : 429 |
Test : SUCCESSBuild number : 612 |
/morph export-build |
Build : SUCCESSBuild number : 780 Triggering tests/morph test |
Exporter Build : ABORTEDBuild number : 432 |
This was aborted by mistake, though there was a duplicate job. I have added it back in queue. |
Exporter Build : SUCCESSBuild number : 433 |
No description provided.