Adding NUCLEO_WB55RG support #9814

- Contains files from STM32Cube_FW_WB_V1.0.0

Align all scatter BLE shared memory declarations.

- Include RTC ll file from hal as in other families - STM32WB: update Flash API driver

- astyle OK - file alignment with other families - HSE, MSI, HSI clock support - LPTICKER with RTC and LPTIM tested

- Need to force ARM packed redefinition - Configure LL stack in LL mode only - Remove warning in shci_tl.c (PLACE_IN_SECTION)

The STM32WB Coridio driver includes: - the Cordio HCI driver handling the reset sequence. During reset sequence the TX POWER level is set and the BD address is defined if found in OTP or option bytes. The rest of the sequence is based on the standard CORDIO HCI driver example. - The Transport Layer part handles sending and receiving messages to the WB controller running on cortex-M0 of the STM32WB target. The messages are shared through shared memory and mailboxes system based on IPCC HW.

- move hw_conf.h file to targets/TARGET_STM/TARGET_STM32WB directory as this is used also out of BLE feature. - create a dedicated hal_deepsleep function as the behavior in WB is a lot different from other existing STM32 targets - update clock tree configuration to directly clock the entire tree @ 32MHz out of HSE. This is needed as we want to let the M0 core running without any change on M0-side of clocks when M4 enters /exits deep sleep.

These files are not BLE specific, but also needed for some clock setting for instance. In order to compile an MBED2 application, we need to move the files.

This is required since PR ARMmbed#9449 commit "Add HAL API for analog in pinmap"

for now based on L4+ cubeMX inputs

In case of mbed2, BLE feature is not built. As there is a MAPPING_TABLE in BLE feature which is not compiled in case of mbed2, the linker reported the below error [ERROR] "C:/Data/Workspace/mbed/BUILD/test/NUCLEO_WB55RG/ARM/MBED_2/ .link_script.sct", line 65 (column 6): Error: L6236E: No section matches selector - no section to be FIRST/LAST. Solution is to check whether BLE is enabled.

There is no need to add FIRST attribute to MAPPING_TABLE as the default ordering is alphabetical order. With this change, we don't have any warning with MBED2 and the sections are properly ordered anyway in BLE cases.

In travis build and in SW4STM32 exporter

Until the CMSIS pack device name is officially deployed. then we'll the name as can be found in Keil CMSIS pack  <device Dname="STM32WB55RGVx"> <memory id="IROM1" start="0x08000000" size="0x001000000" startup="1" default="1" /> <memory id="IRAM1" start="0x20000000" size="0x000040000" init="0" default="1" /> <algorithm name="CMSIS/Flash/STM32WB_M4.FLM" start="0x08000000" size="0x001000000" default="1" /> <feature type="QFP" n="68"/> </device>

also update the copyright year when needed

Need to move stm32wb_HCIDriver.cpp to target specific folder otherwise it could mess up with other STM targets.

as suggested during review, apply same sequence as in: paul-szczepanek-arm@b96c0ac

Issue was seen when running BLE_GAP example from mbed-os-example-ble. In STM32WB, the M0 core cannot be reset except if the whole target is reset. So in case of re-initialization of the BLE stack, the transport layer should not be initialized again. The HCI reset command will do the job.

Because TRNG is a shared resource between the 2 STM32WB cores, SW needs to acquire HW Semaphore before using the resource.

Because FLASH is a shared resource between the 2 STM32WB cores, SW needs to acquire HW Semaphore before using the resource.

Review HSE clock initialization to match with latest CUBE firmware. Also there is no need to set the full clock tree again after deep sleep exit. With this change we get a stable deep sleep mode (when allowed by CORDIO stack).

When doing so, do not disbale GPIO clocks as they may be used by other drivers ! As a result, debug will be disabled by default, but can be enabled by either modifying code or selecting MBED debug profile.

Typically the RTC clock is configured by RTC driver itself. RNG on the other hand is shared with M0+ core and it is expected that M4 turns it on at boot time.

Internal channels use is enabling ADC "internal path" which needs to be disabled after measurement. Same applied here for WB family as was done for others in ARMmbed#10143.

Provide feedback

Saved searches

Use saved searches to filter your results more quickly

Adding NUCLEO_WB55RG support #9814

Adding NUCLEO_WB55RG support #9814

Commits on Mar 29, 2019