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[RISC-V ECLIC] Fix t0 restore when exiting interrupt #277

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Apr 26, 2021
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[RISC-V ECLIC] Fix t0 restore when exiting interrupt #277

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14 changes: 7 additions & 7 deletions os/common/ports/RISCV-ECLIC/compilers/GCC/chcoreasm.S
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Original file line number Diff line number Diff line change
Expand Up @@ -103,6 +103,13 @@
# registers and status csr registers from stack.
# --------------------------------------------------------------------------
.macro RESTORE_CONTEXT
LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0

LOAD ra, 0*REGBYTES(sp)
LOAD tp, 1*REGBYTES(sp)
LOAD t0, 2*REGBYTES(sp)
Expand All @@ -121,13 +128,6 @@
LOAD t5, 15*REGBYTES(sp)
LOAD t6, 16*REGBYTES(sp)

LOAD t0, 17*REGBYTES(sp)
csrw CSR_MEPC, t0
LOAD t0, 18*REGBYTES(sp)
csrw CSR_MCAUSE, t0
LOAD t0, 19*REGBYTES(sp)
csrw CSR_MSUBM, t0

# De-allocate the stack space
addi sp, sp, 20*REGBYTES
.endm
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