[RISC-V ECLIC] Fix t0 restore when exiting interrupt #277
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An oversight when arrangeing the code according to the nucleisys docs, t0 was overriden with the value of msubm and never actually restored. To fix the issue we restore the csrs after the general purpose registers. The offical docs want it the other way around but this should be fine as well, as the interrupts are still globaly disabled at this point.
fpoussin
approved these changes
Apr 26, 2021
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An oversight when arranging the code according to the nucleisys docs, t0 was overriden with the value of msubm and never actually restored. To fix the issue we restore the csrs after the general purpose registers. The offical docs want it the other way around but this should be fine as well, as the interrupts are still globally disabled at this point.