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Software rework #136
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Software rework #136
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robtaylor
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Aug 7, 2025
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@robtaylor can you create the corresponding chipflow-digital-ip PR for this? I don't think it's in place yet |
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Needs to land along with ChipFlow/chipflow-digital-ip#34 and ChipFlow/chipflow-examples#56 |
@@ -487,6 +488,7 @@ def _prepare(self, elaboratable, name="top"): | |||
return fragment.prepare(ports) | |||
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def build(self, elaboratable, name="top"): | |||
warnings.simplefilter(action="ignore", category=UnusedElaboratable) |
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this seems like it might suppress useful warnings sometimes?
from ._annotate import submodule_metadata | ||
from ..software.soft_gen import SoftwareGenerator | ||
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if TYPE_CHECKING: |
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what is this about?
This completely reworks software support for a much simpler model for the user. * User needs add only one line to their design to generate software and one line to associate that software with their rom/flash storage * Drivers now live with their IPs. The driver information is communicated via the signature of the component
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