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v0.9.0 update batch #186

Merged
merged 60 commits into from
Jan 10, 2025
Merged

v0.9.0 update batch #186

merged 60 commits into from
Jan 10, 2025

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soronpo
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@soronpo soronpo commented Sep 26, 2024

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@soronpo
drop output internal read for vhdl.v93
30ee721
@soronpo
cosmetic improvements and documentation to DropOutportRead
66264e7
@soronpo
print only changes
7f36ccd
@soronpo
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into docsu…
48b093f 
…pdate3
@soronpo
turn on stripMargin alignment
5f0ffd6
@soronpo
clearer initFile error message
c41e85d
@soronpo
improve vector type printing
19cc784
@soronpo
trap DFVal implicit conversion type runtime errors
a5f4bdd
@soronpo
relax vector compile-time cell type checks and apply runtime checks
d89dcc4
@soronpo
add support for nvc and iverilog
782a7a4 
fix problems of having parameters and functions outside of verilog modules
@soronpo
add linter tool selection in DFApp
96c063b
@soronpo
No need for specific VivadoOptions
bfdd879
@soronpo
belongs to last commit
3b7bd73
@soronpo
fix verilog 95 sensitivity list separator
35a72aa
@soronpo
add QuestaSim linting support
46832d1 
fix more verilog issues
generalize docExamples linter checks
@soronpo
simplify verilog printing
ce986f3
@soronpo
suppress nvc shared variable warning within Scala execution
ec6c16b
@soronpo
generalized nvc warning suppression to any shared variable name
1f3381e
@soronpo
verilog inputs must have wire modifier
6e0a68b
@soronpo
add Vivado Simulator linting support
d7a7539 
refactor tooling
@soronpo
running tool version checks under a temporary folder
3cb9b9a
@soronpo
suppress nvc warning of existing folder
e91f669
@soronpo
commit and run relative paths where possible
2221feb
@soronpo
fix missing DFApp lint tool selection propagation
d868ccb 
fix DFApp lint tool default printing
@soronpo
change linter warnAsError to fatalWarnings
5aa9d0c
@soronpo
add DFApp fatal warnings options
b8b4608 
force error when warnings are detected in linters that do not have a fatal warnings equivalent
@soronpo
in case a dangling input is allowed, we fix ViaConnection stage to ha…
6312a26 
…ndle it
@soronpo
add dangling input port elaboration checks
24dbf70
@soronpo
add missing period to an error message
812108b
@soronpo
handle vhdl.v93 properly since it does not support unconstrained arrays
b351ca3
soronpo and others added 29 commits October 6, 2024 12:59
@soronpo
allow more FullCompileSpec customization
01cc39e
@soronpo
handle verilog.v2001 and below not supporting global parameters
1918169 
handle vhdl.v93 parametric vector type naming
@soronpo
place Int parameters first in vhdl and verilog, since they may be u…
1685f1f 
…sed for type dimensions.

proper support for vhdl.v93 parameters in vectors
rename `t_vec` to `t_arr`
@soronpo
Questa -pedantic mode has a bug
c0de5bf
@soronpo
fix vhdl vector printing so that AES Cipher compiles successfully in …
4e77203 
…vhdl.v93 and vhdl.v2008
@soronpo
fix vhdl test
e53e31d
@soronpo
handle ports of vectors with design-parameters under vhdl.v93 by inli…
56e8bd8 
…ning the ports
@soronpo
fix vhdl to_slv for vectors with depth > 1
156cd71
@soronpo
fix VHDL print test
42106e9
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
9110233 
…update
ignore cache folder
8cdd9f3
update docs packages
8e55aa7
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
68f5017 
…update
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
196d032 
…update
perform port vector parameter globalization instead of inlining for v…
acb7eee 
…hdl.v93
update Scala to 3.5.2
2b571ee
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
a1465f0 
…update
add copy functions with new references
be7fc26
placing DFStruct given to DFType in a non-conflicting way
9b13c2c
introduce TCConv
9ce91e5
relax sanity refchecks for by-name references
1a3ebce
fix copy of typerefs
4895222
separate public members analysis
6912f70
update globalization with design duplications
d16138c
parameter globalization now keeps the dependecy arithmetics and makin…
add7ff5 
…g vector types identical for VHDL vector assignment
Merge branch 'main' of https://github.com/DFiantHDL/DFiant into tools…
0765ff6 
…update
temporarily disable CipherSpec verilog checks
02fa4cb
CipherSpec split to with/out user opaques
c55e5c5
add a helper summon inline method
c36b913
@soronpo soronpo merged commit d83a22a into main Jan 10, 2025
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@soronpo