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v0.9.0 update batch#186

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soronpo merged 60 commits intomainDFiantHDL/DFHDL:mainfrom toolsupdateDFiantHDL/DFHDL:toolsupdateCopy head branch name to clipboardJan 10, 2025

+2,501-646

Commits

Commits on Sep 12, 2024

• drop output internal read for vhdl.v93

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• cosmetic improvements and documentation to DropOutportRead

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Commits on Sep 20, 2024

• print only changes

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• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into docsupdate3

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Commits on Sep 25, 2024

• turn on stripMargin alignment

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• clearer initFile error message

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• improve vector type printing

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• trap DFVal implicit conversion type runtime errors

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• relax vector compile-time cell type checks and apply runtime checks

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Commits on Sep 26, 2024

• add support for nvc and iverilog

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Commits on Sep 29, 2024

• add linter tool selection in DFApp

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Commits on Sep 30, 2024

• No need for specific VivadoOptions

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• belongs to last commit

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• fix verilog 95 sensitivity list separator

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Commits on Oct 1, 2024

• add QuestaSim linting support

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• simplify verilog printing

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• suppress nvc shared variable warning within Scala execution

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• generalized nvc warning suppression to any shared variable name

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Commits on Oct 2, 2024

• verilog inputs must have wire modifier

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Commits on Oct 3, 2024

• add Vivado Simulator linting support

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• running tool version checks under a temporary folder

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• suppress nvc warning of existing folder

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• commit and run relative paths where possible

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• fix missing DFApp lint tool selection propagation

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• change linter warnAsError to fatalWarnings

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Commits on Oct 4, 2024

• add DFApp fatal warnings options

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• in case a dangling input is allowed, we fix ViaConnection stage to handle it

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• add dangling input port elaboration checks

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• add missing period to an error message

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Commits on Oct 6, 2024

• handle vhdl.v93 properly since it does not support unconstrained arrays

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• suppress vivado warnings of missing initial parameter values

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• allow more FullCompileSpec customization

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Commits on Oct 7, 2024

• handle verilog.v2001 and below not supporting global parameters

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• place Int parameters first in vhdl and verilog, since they may be used for type dimensions.

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Commits on Oct 8, 2024

• Questa -pedantic mode has a bug

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• fix vhdl vector printing so that AES Cipher compiles successfully in vhdl.v93 and vhdl.v2008

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• fix vhdl test

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Commits on Oct 9, 2024

• handle ports of vectors with design-parameters under vhdl.v93 by inlining the ports

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• fix vhdl to_slv for vectors with depth > 1

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Commits on Oct 14, 2024

• fix VHDL print test

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Commits on Oct 22, 2024

• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into toolsupdate

  

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• ignore cache folder

  

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• update docs packages

  

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Commits on Nov 25, 2024

• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into toolsupdate

  

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Commits on Dec 5, 2024

• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into toolsupdate

  

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Commits on Dec 7, 2024

• perform port vector parameter globalization instead of inlining for vhdl.v93

  

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• update Scala to 3.5.2

  

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• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into toolsupdate

  

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• add copy functions with new references

  

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Commits on Dec 23, 2024

• placing DFStruct given to DFType in a non-conflicting way

  

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Commits on Dec 24, 2024

• introduce TCConv

  

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Commits on Dec 30, 2024

• relax sanity refchecks for by-name references

  

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• fix copy of typerefs

  

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• separate public members analysis

  

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• update globalization with design duplications

  

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Commits on Jan 10, 2025

• parameter globalization now keeps the dependecy arithmetics and making vector types identical for VHDL vector assignment

  

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• Merge branch 'main' of https://github.com/DFiantHDL/DFiant into toolsupdate

  

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• temporarily disable CipherSpec verilog checks

  

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• CipherSpec split to with/out user opaques

  

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• add a helper summon inline method

  

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