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2. Front End
The five AFE chips output data serially over 8 LVDS pairs along with a high speed clock (DCLK) and frame marker (FCLK). As the ADC sample rate is 62.5MHz and the data is 14 bit DDR, this means that DCLK is 437.5MHz and the data rate per LVDS pair is 875Mbps. In the FPGA these serial streams must be reliabliy converted back to 14 bit parallel buses in a common clock domain.
The alignment scheme used here is a bit simpler than the "typical" methods used in the Xilinx application notes. The reason for this is that in our case the FPGA also supplies the reference clock to the AFE chips. Therefore, each AFE is frequency locked to the master FPGA clock of 62.5MHz. This fact simplifies the front end alignment logic and eliminates a whole level of clock domain crossing in our case. Furthermore, the high speed forwarded clock from the AFE chip (DCLK) is not even used; rather this high speed clock is generated internally in the FPGA instead.
The front end alignment logic first adjusts (IDELAYE2) the input data streams so that the high speed sample clock is in the optimal center of the eye. Then using the known FCLK pattern the serial to parallel shift register logic (ISERDESE2) is BITSLIPed until the 14 bit parallel data is properly framed. The assumption here is that whatever adjustments were made to properly recover the frame pattern (which is always present) is applied to all other data streams from a given AFE.
This scheme works for all 40 AFE channels and requires no user intervention aside from a soft reset after the FPGA is programmed.
The output of the front end logic is 40 14-bit data buses synchronized to the master 62.5 MHz clock domain.
Spy buffers are triggered by an external positive input pulse (optically isolated) or by writing to a control register in the GbE address space.
When triggered, the spy buffers will capture 64 pre-trigger samples followed by 4032 samples on EACH AFE channel. These buffers are memory mapped into the GBE internal address space and then can be read out at any time. Note that the Spy Buffer trigger is totally separate from the trigger condition in the self-triggered core logic.
Output spy buffers capture the data that the core is sending on the DAQ0 output link. This spy buffer is 32 bits wide and 4k deep. It is triggered along with the input spy buffers.