6. Self Triggered Sender
The core logic contains the sender firmware. The senders take the raw AFE data (after it has been aligned to the master clock) and form output records. Output records are sent downstream to DAQ over high speed serial links.
The self triggered sender is built upon a modular approach. The STC module monitors a single AFE data stream. Each STC module continuously monitors the data stream from an input channel. It automatically computes the average signal baseline level over 256 samples. The baseline level is reported in the output record header. The baseline is reported as a 14 bit UNSIGNED value.
The user supplies the relative threshold value as a 14 bit UNSIGNED number. The absolute trig_threshold is defined as average_baseline - user_threshold. These arithmetic operations are all done assuming UNSIGNED values. The trigger condition is defined simply as one sample above trig_threshold followed by two samples BELOW the trig_threshold. This is because the expected pulse is NEGATIVE GOING.
Once a trigger condition is satisfied, the STC module waits for 64 clock cycles, then grabs the next 1024 samples (including 64 pre-trigger samples), forms an output frame around this data, and stores this frame in a FIFO. This FIFO is deep enough to store ~8.9 events.
Once the STC module is triggered it begins to capture the pre- and post- trigger samples. If during this time another trigger condition occurs, it is currently ignored, as it is assumed that this condition is going to be captured anyway. In a future version we may change this to support overlapping or re-trigger functionality.
On the sender backend, a state machine scans across 10 modules looking to see who has an output record ready to send in the FIFO. In a round robin manner these STC modules are selected to dump data to the output link to FELIX. And the process repeats. The current design has 10 input modules feeding one output: channels 0-9 feed into output 0, channels 10-19 feed into output 1, and so on.
