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i#2626 fp/simd encode: Add support for most FP Neon instructions.
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This patch adds encoding & decoding support for most arithmetic FP Neon
instructions. The structure of the generated macros and tests follows
the style of #2896.

codec.txt contains comments if not all encodings of an instruction are
supported yet. Also missing are the Arm v8.3-a FCADD and FCMLA
instructions, because their rotation arguments require a bit of special
handling to get nice macros.

Issue #2626

Change-Id: I8c3a8ac3e03d9b466c1872ed5382639b746092b2
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@fhahn
fhahn committed Apr 23, 2018
1 parent 60203db commit 83f8cba
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Showing 6 changed files with 2,543 additions and 111 deletions.
12 changes: 12 additions & 0 deletions core/arch/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -1112,6 +1112,18 @@ encode_opnd_float_reg5(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *en
return encode_opnd_float_reg(5, opnd, enc_out);
}

static inline bool
decode_opnd_float_reg10(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
return decode_opnd_float_reg(10, enc, opnd);
}

static inline bool
encode_opnd_float_reg10(uint enc, int opcode, byte *pc, opnd_t opnd, OUT uint *enc_out)
{
return encode_opnd_float_reg(10, opnd, enc_out);
}

static inline bool
decode_opnd_float_reg16(uint enc, int opcode, byte *pc, OUT opnd_t *opnd)
{
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178 changes: 175 additions & 3 deletions core/arch/aarch64/codec.txt
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Original file line number Diff line number Diff line change
Expand Up @@ -60,6 +60,7 @@
---------------------------xxxxx h0 # H register
--------xx-----------------xxxxx float_reg0 # H, S or D register including type for FP instruction
--------xx------------xxxxx----- float_reg5 # H, S or D register including type for FP instruction
--------xx-------xxxxx---------- float_reg10 # H, S or D register including type for FP instruction
--------xx-xxxxx---------------- float_reg16 # H, S or D register including type for FP instruction
---------------------------xxxxx s0 # S register
---------------------------xxxxx d0 # D register
Expand Down Expand Up @@ -945,17 +946,188 @@ x101101011000000000101xxxxxxxxxx cls wx0 : wx5
1101101011000000000011xxxxxxxxxx rev x0 : x5

# Data Processing - Scalar Floating-Point and Advanced SIMD
# FABD
0x101110110xxxxx000101xxxxxxxxxx fabd dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx110101xxxxxxxxxx fabd dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/sub/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/sub/fp/sisd

# FABS (scalar)
00011110xx100000110000xxxxxxxxxx fabs float_reg0 : float_reg5

# FACGE
0x101110010xxxxx001011xxxxxxxxxx facge dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx111011xxxxxxxxxx facge dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp/sisd

# FACGT
0x101110110xxxxx001011xxxxxxxxxx facgt dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx111011xxxxxxxxxx facgt dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp/sisd

# FADD (vector)
0x001110010xxxxx000101xxxxxxxxxx fadd dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx110101xxxxxxxxxx fadd dq0 : dq5 dq16 fsz
0x001110010xxxxx000101xxxxxxxxxx fadd dq0 : dq5 dq16 fsz16

# FADD (scalar)
00011110xx1xxxxx001010xxxxxxxxxx fadd float_reg0 : float_reg5 float_reg16
00011110xx1xxxxx001010xxxxxxxxxx fadd float_reg0 : float_reg5 float_reg16

# FADDP (vector)
0x101110010xxxxx000101xxxxxxxxxx faddp dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx110101xxxxxxxxxx faddp dq0 : dq5 dq16 fsz

# FCMEQ (register)
0x001110010xxxxx001001xxxxxxxxxx fcmeq dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx111001xxxxxxxxxx fcmeq dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp/sisd

# FCMGE (register)
0x101110010xxxxx001001xxxxxxxxxx fcmge dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx111001xxxxxxxxxx fcmge dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp/sisd

# FCMGT (register)
0x101110110xxxxx001001xxxxxxxxxx fcmgt dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx111001xxxxxxxxxx fcmgt dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/cmp/fp/sisd

# FDIV (vector)
0x101110010xxxxx001111xxxxxxxxxx fdiv dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx111111xxxxxxxxxx fdiv dq0 : dq5 dq16 fsz

# FDIV (scalar)
00011110xx1xxxxx000110xxxxxxxxxx fdiv float_reg0 : float_reg5 float_reg16

# FMADD
00011111xx0xxxxx0xxxxxxxxxxxxxxx fmadd float_reg0 : float_reg5 float_reg16 float_reg10

# FMAX (vector)
0x001110010xxxxx001101xxxxxxxxxx fmax dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx111101xxxxxxxxxx fmax dq0 : dq5 dq16 fsz

# FMAX (scalar)
00011110xx1xxxxx010010xxxxxxxxxx fmax float_reg0 : float_reg5 float_reg16

# FMAXNM (vector)
0x001110010xxxxx000001xxxxxxxxxx fmaxnm dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx110001xxxxxxxxxx fmaxnm dq0 : dq5 dq16 fsz

# FMAXNM (scalar)
00011110xx1xxxxx011010xxxxxxxxxx fmaxnm float_reg0 : float_reg5 float_reg16

# FMAXNMP (vector)
0x101110010xxxxx000001xxxxxxxxxx fmaxnmp dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx110001xxxxxxxxxx fmaxnmp dq0 : dq5 dq16 fsz

# FMAXP (vector)
0x101110010xxxxx001101xxxxxxxxxx fmaxp dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx111101xxxxxxxxxx fmaxp dq0 : dq5 dq16 fsz

# FMIN (vector)
0x001110110xxxxx001101xxxxxxxxxx fmin dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011101x1xxxxx111101xxxxxxxxxx fmin dq0 : dq5 dq16 fsz

# FMIN (scalar)
00011110xx1xxxxx010110xxxxxxxxxx fmin float_reg0 : float_reg5 float_reg16

# FMINNM (vector)
0x001110110xxxxx000001xxxxxxxxxx fminnm dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011101x1xxxxx110001xxxxxxxxxx fminnm dq0 : dq5 dq16 fsz

# FMINNM (scalar)
00011110xx1xxxxx011110xxxxxxxxxx fminnm float_reg0 : float_reg5 float_reg16

# FMINNMP (vector)
0x101110110xxxxx000001xxxxxxxxxx fminnmp dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx110001xxxxxxxxxx fminnmp dq0 : dq5 dq16 fsz

# FMINP (vector)
0x101110110xxxxx001101xxxxxxxxxx fminp dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011101x1xxxxx111101xxxxxxxxxx fminp dq0 : dq5 dq16 fsz

# FMLA (vector)
0x001110010xxxxx000011xxxxxxxxxx fmla dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx110011xxxxxxxxxx fmla dq0 : dq5 dq16 fsz

# FMLS (vector)
0x001110110xxxxx000011xxxxxxxxxx fmls dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011101x1xxxxx110011xxxxxxxxxx fmls dq0 : dq5 dq16 fsz

# FMOV (register)
00011110xx100000010000xxxxxxxxxx fmov float_reg0 : float_reg5

# FMSUB
00011111xx0xxxxx1xxxxxxxxxxxxxxx fmsub float_reg0 : float_reg5 float_reg16 float_reg10

# FMUL (vector)
0x101110010xxxxx000111xxxxxxxxxx fmul dq0 : dq5 dq16 fsz16
0x101110010xxxxx000111xxxxxxxxxx fmul dq0 : dq5 dq16 fsz16 # Armv8.2
0x1011100x1xxxxx110111xxxxxxxxxx fmul dq0 : dq5 dq16 fsz

# FMUL (scalar)
00011110xx1xxxxx000010xxxxxxxxxx fmul float_reg0 : float_reg5 float_reg16

# FMULX
0x001110010xxxxx000111xxxxxxxxxx fmulx dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx110111xxxxxxxxxx fmulx dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp16/extended/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/mul/fp/extended/sisd

# FNEG (scalar)
00011110xx100001010000xxxxxxxxxx fneg float_reg0 : float_reg5

# FNMADD
00011111xx1xxxxx0xxxxxxxxxxxxxxx fnmadd float_reg0 : float_reg5 float_reg16 float_reg10

# FNMSUB
00011111xx1xxxxx1xxxxxxxxxxxxxxx fnmsub float_reg0 : float_reg5 float_reg16 float_reg10

# FNMUL (scalar)
00011110xx1xxxxx100010xxxxxxxxxx fnmul float_reg0 : float_reg5 float_reg16

# FRECPS
0x001110010xxxxx001111xxxxxxxxxx frecps dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011100x1xxxxx111111xxxxxxxxxx frecps dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/recps-fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/recps/sisd

# FRINTA (scalar)
00011110xx100110010000xxxxxxxxxx frinta float_reg0 : float_reg5

# FRINTI (scalar)
00011110xx100111110000xxxxxxxxxx frinti float_reg0 : float_reg5

# FRINTM (scalar)
00011110xx100101010000xxxxxxxxxx frintm float_reg0 : float_reg5

# FRINTN (scalar)
00011110xx100100010000xxxxxxxxxx frintn float_reg0 : float_reg5

# FRINTP (scalar)
00011110xx100100110000xxxxxxxxxx frintp float_reg0 : float_reg5

# FRINTX (scalar)
00011110xx100111010000xxxxxxxxxx frintx float_reg0 : float_reg5

# FRINTZ (scalar)
00011110xx100101110000xxxxxxxxxx frintz float_reg0 : float_reg5

# FRSQRTS
0x001110110xxxxx001111xxxxxxxxxx frsqrts dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011101x1xxxxx111111xxxxxxxxxx frsqrts dq0 : dq5 dq16 fsz
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/rsqrts-fp16/sisd
# Missing encoding: aarch64/instrs/vector/arithmetic/binary/uniform/rsqrts/sisd

# FSQRT (scalar)
00011110xx100001110000xxxxxxxxxx fsqrt float_reg0 : float_reg5

# FSUB (vector)
0x001110110xxxxx000101xxxxxxxxxx fsub dq0 : dq5 dq16 fsz16 # Armv8.2
0x0011101x1xxxxx110101xxxxxxxxxx fsub dq0 : dq5 dq16 fsz

# FSUB (scalar)
00011110xx1xxxxx001110xxxxxxxxxx fsub float_reg0 : float_reg5 float_reg16
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