i#2626 fp/simd encode: Add support for vector and scalar FMUL. (#2896)

This uses the encoding scheme introduced in #2811.

Everything expect the tests are auto-generated now.

core/arch/aarch64/codec.txt

@@ -952,3 +952,10 @@ x101101011000000000101xxxxxxxxxx  cls     wx0 : wx5
 
 # FADD (scalar)
 00011110xx1xxxxx001010xxxxxxxxxx fadd float_reg0 : float_reg5 float_reg16
+
+# FMUL (vector)
+0x101110010xxxxx000111xxxxxxxxxx     fmul dq0 : dq5 dq16 fsz16
+0x1011100x1xxxxx110111xxxxxxxxxx     fmul dq0 : dq5 dq16 fsz
+
+# FMUL (scalar)
+00011110xx1xxxxx000010xxxxxxxxxx     fmul float_reg0 : float_reg5 float_reg16

core/arch/aarch64/encode_gen.h

@@ -3244,7 +3244,7 @@ encode_opndsgen_1c000000(byte *pc, instr_t *instr, uint enc, decode_info_t *di)
 }
 
 static uint
-encode_opndsgen_1e202800(byte *pc, instr_t *instr, uint enc, decode_info_t *di)
+encode_opndsgen_1e200800(byte *pc, instr_t *instr, uint enc, decode_info_t *di)
 {
     int opcode = instr->opcode;
     uint dst0 = 0, src0 = 0, src1 = 0;
@@ -6723,7 +6723,15 @@ encoder(byte *pc, instr_t *instr, decode_info_t *di)
         enc = encode_opndsgen_0e401400(pc, instr, 0x0e401400, di);
         if (enc != ENCFAIL)
             return enc;
-        return encode_opndsgen_1e202800(pc, instr, 0x1e202800, di);
+        return encode_opndsgen_1e200800(pc, instr, 0x1e202800, di);
+    case OP_fmul:
+        enc = encode_opndsgen_0e20d400(pc, instr, 0x2e20dc00, di);
+        if (enc != ENCFAIL)
+            return enc;
+        enc = encode_opndsgen_0e401400(pc, instr, 0x2e401c00, di);
+        if (enc != ENCFAIL)
+            return enc;
+        return encode_opndsgen_1e200800(pc, instr, 0x1e200800, di);
     case OP_hlt:
         return encode_opndsgen_d4000001(pc, instr, 0xd4400000, di);
     case OP_hvc:

core/arch/aarch64/instr_create.h

@@ -47,18 +47,36 @@
  */
 #define FSZ_HALF 1
 
+/**
+ * Operand indicating half-precision floating point vector elements for the
+ * other operands of the containing instruction.
+ */
+#define OPND_CREATE_HALF() OPND_CREATE_INT8(FSZ_HALF)
+
 /**
  * Used in an additional immediate source operand to a vector operation, denotes
  * single-precision floating point vector elements. See \ref sec_IR_AArch64.
  */
 #define FSZ_SINGLE 2
 
+/**
+ * Operand indicating single-precision floating point vector elements for the
+ * other operands of the containing instruction.
+ */
+#define OPND_CREATE_SINGLE() OPND_CREATE_INT8(FSZ_SINGLE)
+
 /**
  * Used in an additional immediate source operand to a vector operation, denotes
  * double-precision floating point vector elements. See \ref sec_IR_AArch64.
  */
 #define FSZ_DOUBLE 3
 
+/**
+ * Operand indicating double-precision floating point vector elements for the
+ * other operands of the containing instruction.
+ */
+#define OPND_CREATE_DOUBLE() OPND_CREATE_INT8(FSZ_DOUBLE)
+
 
 /**
  * @file dr_ir_macros_aarch64.h
@@ -557,6 +575,29 @@
 #define INSTR_CREATE_sub_shimm(dc, rd, rn, rm_or_imm, sht, sha) \
   INSTR_CREATE_sub_shift(dc, rd, rn, rm_or_imm, sht, sha)
 
+
+/**
+ * Creates a FMUL vector instruction.
+ * \param dc     The void * dcontext used to allocate memory for the instr_t.
+ * \param Rd     The output register.
+ * \param Rm     The first input register.
+ * \param Rn     The second input register.
+ * \param width  The vector element width. Use either OPND_CREATE_HALF(),
+ *               OPND_CREATE_SINGLE() or OPND_CREATE_DOUBLE().
+ */
+#define INSTR_CREATE_fmul_vector(dc, Rd, Rm, Rn, width) \
+    instr_create_1dst_3src(dc, OP_fmul, Rd, Rm, Rn, width)
+
+/**
+ * Creates a FMUL floating point instruction.
+ * \param dc   The void * dcontext used to allocate memory for the instr_t.
+ * \param Rd   The output register.
+ * \param Rm   The first input register.
+ * \param Rn   The second input register.
+ */
+#define INSTR_CREATE_fmul_scalar(dc, Rd, Rm, Rn) \
+    instr_create_1dst_2src(dc, OP_fmul, Rd, Rm, Rn)
+
 /* DR_API EXPORT END */
 
 #endif /* INSTR_CREATE_H */