ARM suite test regressions: api.disA32, api.disT32, many more #3699
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I'm assuming these regressions have happened because we don't have AArch32 precommit testing in the same way we have for AArch64? |
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Note: in a recent debug run In a recent release run we observe |
That's my assumption, but I wouldn't have expected the ARM encoder/decoder tests to have broken. Hopefully it's something simple. |
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The log message for c76c485 (Oct 2021) says: That change is responsible for most of the The other |
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I did a bisection on |
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Yes, I did see (A spurious retcode of length 8 bytes happens to be harmless because there are a couple of items on the stack beyond the |
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In an Perhaps it's obvious in hindsight was was happening but I had to do stuff like insert home-made
So I changed (In order to build the tests I also had to add a bogus definition of Question for @derekbruening: Is changing (Since DynamoRIO has been broken on 32-bit ARM hardware since 2019 there's perhaps not a huge amount of interest in it so we probably can't invest a huge amount of effort into it so an easy fix would be preferred!) |
The definition did not agree with the Linux kernel's definition. There is a retcode field in sigframe, but not in rt_sigframe. Issue: #3699 Change-Id: Icbdd204a021778e329d5f5831933debda4bd9dd4
The definition did not agree with the Linux kernel's definition. There is a retcode field in sigframe, but not in rt_sigframe. This change made the previously failing common.segfault test pass in a Debian 10 container running under a 64-bit 5.4.47 kernel on Cortex-A72 hardware. Issue: #3699
Maybe that is the simplest rather than having to find all C++ uses and replacing with |
Add previously missing asm for 32-bit ARM clone3 system call. Issue: #3699
dd1589c modified dstack_offs in insert_push_all_registers without generating an instruction that modifies SP. So add a SUB SP, SP, #4 there, and a corresponding ADD SP, SP, #4 in insert_pop_all_registers. This made the test client.cleancallparams pass. Issue: #3699 Change-Id: I25d2a22e7feb7bc1227aeec74847c80754eae254
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With 73b1df1 plus a few changes that have not yet been merged, namely:
in an AArch32 Debian 10 container under a 64-bit 5.4.47 Linux kernel running on Cortex-A72 I got 47 tests failed out of 298: |
Some C++ library functions require 8-byte alignment. This made the test drcacheoff.simple pass on 32-bit ARM. Issue: #3699 Change-Id: I507833f3367508fd512ee2d1fa272b04203bfff1
Some C++ library functions require 8-byte alignment. This made the test drcacheoff.simple pass on 32-bit ARM. Issue: #3699
On ARM/AArch64 not all MRS/MSR instructions operate on aflags, and on ARM the register source operand of MSR, if there is one, is the second operand. This change made the test sample.memval_simple pass on 32-bit ARM. Issue: #3699 Change-Id: I9a04273ed0507c0f8cccd636fdbc0aff1b5bf36d
On ARM/AArch64 not all MRS/MSR instructions operate on aflags, and on ARM the register source operand of MSR, if there is one, is the second operand. This change made the test sample.memval_simple pass on 32-bit ARM. (But client.drreg-test does not yet pass.) Issue: #3699
ef4482e caused a few additional failures. In particular, the child of a clone3 system call started with the register values shifted: R2 got the value that should be in R1 and so on. That caused the test linux.clone to fail. It turns out that some callers of insert_{push,pop}_all_registers expect that an unpadded priv_mcontext_t will be pushed/popped. Moving the 4-byte padding to above the struct instead of below it makes some tests pass but breaks others. So we add some padding to priv_mcontext_t itself, changing its size from 324 to 328. It will probably run slightly faster with the struct 8-byte aligned. Update insert_{push,pop}_all_registers and arm.asm for the new struct layout, with some additional changes to arm.asm: + Delete irrelevant X64 macros. + Document the macros more clearly (they can be found with grep). + Change SP only at start and end of function (standard practice, makes debugging easier). + Avoid writing below SP (compatible with signal handlers). Issue: #3699 Change-Id: I4977c5bf42e349d1085dbdecf3428e83a4a2399c
ef4482e caused a few additional failures. In particular, the child of a clone3 system call started with the register values shifted: R2 got the value that should be in R1 and so on. That caused the test linux.clone to fail. It turns out that some callers of insert_{push,pop}_all_registers expect that an unpadded priv_mcontext_t will be pushed/popped. Moving the 4-byte padding to above the struct instead of below it makes some tests pass but breaks others. So we add some padding in the middle of priv_mcontext_t, changing its size from 324 to 328. It will probably run slightly faster with the struct (and particularly the field "simd") 8-byte aligned. Update insert_{push,pop}_all_registers and arm.asm for the new struct layout, with some additional changes to arm.asm: + Delete irrelevant X64 macros. + Document the macros more clearly (they can be found with grep). + Change SP only at start and end of function (standard practice, makes debugging easier). + Avoid writing below SP (compatible with signal handlers). This change breaks compatibility so the version is increased to 11.90. Issue: #3699
This makes the test code_api|linux.signal_pre_syscall pass. Issue: #3699 Change-Id: I3c6f51b36ee68f2e32b931e528c064a859aa52b3
This makes the test code_api|linux.signal_pre_syscall pass. Issue: #3699
Small changes to make these tests pass on 32-bit Arm: + code_api|tool.drcacheoff.altbindir + code_api|tool.drcacheoff.legacy-int-offs Issue: #3699 Change-Id: I89035440654c536ecb6d63d64a1c2a7999f34068
We did not have ARM tests being run for a while. Now that we have a CDash machine back up, I compared its debug run yesterday to the most recent on that same machine name from April 2018:
http://dynamorio.org/CDash/viewTest.php?buildid=35255
http://dynamorio.org/CDash/viewTest.php?buildid=44194
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