Fix wrong source operand decoding for SP vadd.f32 #2967
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- Change ARM table for vadd.f32 to use the correct decoding format for the second source register of single precision floating point operations. Specifically use WCd format instead of the VCd, which was wrong.
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I'm trying to do for the first time the non-member pull request review. Please let me know if I'm doing it right. Cheers. |
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run arm tests |
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Thank you for the patch. (Unfortunately we did not finish adding all the ARM decoding tests we wanted (#1686) and did not catch these earlier.)
| @@ -504,7 +504,7 @@ const instr_info_t T32_ext_opc4fpA[][3] = { | |||
| {INVALID, 0xee200a10, "(bad)", xx, xx, xx, xx, xx, no, x, NA}, | |||
| {OP_vnmul_f32,0xee200a40, "vnmul.f32", WBd, xx, WAd, WCd, xx, vfp, x, END_LIST}, | |||
| }, { /* 3 */ | |||
| {OP_vadd_f32, 0xee300a00, "vadd.f32", WBd, xx, WAd, VCd, xx, vfp, x, END_LIST}, | |||
| {OP_vadd_f32, 0xee300a00, "vadd.f32", WBd, xx, WAd, WCd, xx, vfp, x, END_LIST}, | |||
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I believe the entries in table_a32_pred.c are also incorrect. Could you fix those as well?
$ git grep 'W.*xx.*W.* V'
core/arch/arm/table_a32_pred.c: {OP_vadd_f32, 0x0e300a00, "vadd.f32", WBd, xx, WAd, VCd, xx, pred|vfp, x, END_LIST},
core/arch/arm/table_a32_pred.c: {OP_vadd_f32, 0x0e700a00, "vadd.f32", WBd, xx, WAd, VCd, xx, pred|vfp, x, DUP_ENTRY},
core/arch/arm/table_t32_coproc.c: {OP_vadd_f32, 0xee300a00, "vadd.f32", WBd, xx, WAd, VCd, xx, vfp, x, END_LIST},
core/arch/arm/table_t32_coproc.c: {OP_vadd_f32, 0xee700a00, "vadd.f32", WBd, xx, WAd, VCd, xx, vfp, x, DUP_ENTRY},
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Done! I've pushed another commit.
derekbruening
approved these changes
Apr 27, 2018
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run arm tests |
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the second source register of single precision floating point operations.
Specifically use WCd format instead of the VCd, which was wrong.