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AArch64 decoder/encoder improvements #4393
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There are some script to auto-generate parts of codec.txt, tests and instr_create.h macros from an ISA description on the branch: https://github.com/DynamoRIO/dynamorio/commits/project-aarch64-generate-patterns Not sure how well they aged though. |
AssadHashmi
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AssadHashmi
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The current methods of defining and generating encode and decode functionality are not scalable for implementing support of ISA versions after v8.0 This patch splits up the codec.txt file into codec_<version>.txt files and opnd_defs.txt. Generated code is now split out into ISA version specific files. Tests and related files have not been split up yet. That will happen as part of new ISA version implementations. Issue: #5326, #4393
AssadHashmi
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The current methods of defining and generating encode and decode functionality are not scalable for implementing support of ISA versions after v8.0 This patch splits up the codec.txt file into codec_<version>.txt files and opnd_defs.txt. Generated code is now split out into ISA version specific files. Tests and related files have not been split up yet. That will happen as part of new ISA version implementations. Issue: #5326, #4393
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This patch is an example of the code which will be generated from a machine readable specification (MRS) to decode and encode AArch64 instructions from v8.1 onwards. It is provided for review and discussion purposes, in order to resolve any issues which may arise and to make visible what changes to expect. This patch does not include the MRS, the parser or generator, just an example of the target code which we intend to generate, based on the v8.1 SQRDMLAH instruction. Issue: #4393, #3044, #2626
AssadHashmi
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This patch is an example of the code which will be generated from a machine readable specification (MRS) to decode and encode AArch64 instructions from v8.1 onwards. It is provided for review and discussion purposes, in order to resolve any issues which may arise and to make visible what changes to expect. This patch does not include the MRS, the parser or generator, just an example of the target code which we intend to generate, based on the v8.1 SQRDMLAH instruction. Issue: #4393, #3044, #2626
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dolanzhao
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This patch modifies the testing macros to reduce the need to instantiate variables in each test. It also predefines some lists of registers that are commonly used issues: #4393 Change-Id: I33be226fdb73b9c178c2ba1d7047bd8db047dbdd
joshua-warburton
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This patch modifies the testing macros to reduce the need to instantiate variables in each test. It also predefines some lists of registers that are commonly used issues: #4393
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Many immediate value operands follow the naming convention: <type>imm<size>_<lsb> So you would expect fpimm13 to be a 13-bit floating-point immediate value. It is actually an 8-bit floating-point immediate value at bit 13 so following the above naming convention it should be called fpimm8_13. Issues: #4393
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This pulls out code for encoding and decoding 8-bit floating-point immediate values into helper functions that can be re-used for future instructions with similar operands. This commit also renames the fpimm13 operand to fpimm8_13 Many immediate value operands follow the naming convention: <type>imm<size>[_<lsb>] So you would expect fpimm13 to be a 13-bit floating-point immediate value. It is actually an 8-bit floating-point immediate value at bit 13 so following the above naming convention it should be called fpimm8_13. Issues: #4393
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This pulls out code for encoding and decoding 8-bit floating-point immediate values into helper functions that can be re-used for future instructions with similar operands. This commit also renames the fpimm13 operand to fpimm8_13 Many immediate value operands follow the naming convention: <type>imm<size>[_<lsb>] So you would expect fpimm13 to be a 13-bit floating-point immediate value. It is actually an 8-bit floating-point immediate value at bit 13 so following the above naming convention it should be called fpimm8_13. Issues: #4393
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The current method of generating decode/encode functions based on the
codec.txt
bitmap format has limitations in terms of:DC
andIC
based onSYS
, andPRFM
. See [AArch64] Split OP_prfm opcode, or provide named constants for the sub-opcode immediate operand #4388 and discussion at i#4329: Implement effective address of DC cache operations #4386 (comment).The proposal is to use the publicly available XML specifications to replace
codec.txt
as the source from which to generate decode/encode functionality. Useful links:https://alastairreid.github.io/ARM-v8a-xml-release/
https://developer.arm.com/architectures/instruction-sets/base-isas/a64
https://github.com/alastairreid/mra_tools
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