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i#2626: Add AARCH64 Attribute registers to the DR_REG enum #6835

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Jun 4, 2024
Merged

i#2626: Add AARCH64 Attribute registers to the DR_REG enum #6835

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i#2626: Add AARCH64 Attribute registers to the DR_REG enum
philramsey-arm Jun 3, 2024
a929e23
Merge branch 'master' into i#2626-add_aarch64_attrib_registers
philramsey-arm Jun 4, 2024
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24 changes: 24 additions & 0 deletions core/ir/aarch64/codec.c
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Original file line number Diff line number Diff line change
Expand Up @@ -283,6 +283,18 @@ decode_sysreg(uint imm15)
{
reg_t sysreg;
switch (imm15) {
case 0x4000: sysreg = DR_REG_MIDR_EL1; break;
case 0x4005: sysreg = DR_REG_MPIDR_EL1; break;
case 0x4006: sysreg = DR_REG_REVIDR_EL1; break;
case 0x4020: sysreg = DR_REG_ID_AA64PFR0_EL1; break;
case 0x4021: sysreg = DR_REG_ID_AA64PFR1_EL1; break;
case 0x4024: sysreg = DR_REG_ID_AA64ZFR0_EL1; break;
case 0x4028: sysreg = DR_REG_ID_AA64DFR0_EL1; break;
case 0x4030: sysreg = DR_REG_ID_AA64ISAR0_EL1; break;
case 0x4031: sysreg = DR_REG_ID_AA64ISAR1_EL1; break;
case 0x4032: sysreg = DR_REG_ID_AA64ISAR2_EL1; break;
case 0x4039: sysreg = DR_REG_ID_AA64MMFR1_EL1; break;
case 0x403A: sysreg = DR_REG_ID_AA64MMFR2_EL1; break;
case 0x5a10: sysreg = DR_REG_NZCV; break;
case 0x5a20: sysreg = DR_REG_FPCR; break;
case 0x5a21: sysreg = DR_REG_FPSR; break;
Expand Down Expand Up @@ -406,6 +418,18 @@ encode_sysreg(OUT uint *imm15, opnd_t opnd)
{
if (opnd_is_reg(opnd)) {
switch (opnd_get_reg(opnd)) {
case DR_REG_MIDR_EL1: *imm15 = 0x4000; break;
case DR_REG_MPIDR_EL1: *imm15 = 0x4005; break;
case DR_REG_REVIDR_EL1: *imm15 = 0x4006; break;
case DR_REG_ID_AA64PFR0_EL1: *imm15 = 0x4020; break;
case DR_REG_ID_AA64PFR1_EL1: *imm15 = 0x4021; break;
case DR_REG_ID_AA64ZFR0_EL1: *imm15 = 0x4024; break;
case DR_REG_ID_AA64DFR0_EL1: *imm15 = 0x4028; break;
case DR_REG_ID_AA64ISAR0_EL1: *imm15 = 0x4030; break;
case DR_REG_ID_AA64ISAR1_EL1: *imm15 = 0x4031; break;
case DR_REG_ID_AA64ISAR2_EL1: *imm15 = 0x4032; break;
case DR_REG_ID_AA64MMFR1_EL1: *imm15 = 0x4039; break;
case DR_REG_ID_AA64MMFR2_EL1: *imm15 = 0x403A; break;
case DR_REG_NZCV: *imm15 = 0x5a10; break;
case DR_REG_FPCR: *imm15 = 0x5a20; break;
case DR_REG_FPSR: *imm15 = 0x5a21; break;
Expand Down
21 changes: 19 additions & 2 deletions core/ir/aarch64/encode.c
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Original file line number Diff line number Diff line change
Expand Up @@ -118,7 +118,9 @@ const char *const reg_names[] = {
"p10", "p11", "p12", "p13", "p14", "p15",
"ffr",

"cntvct_el0",
"cntvct_el0", "id_aa64isar0_el1", "id_aa64isar1_el1", "id_aa64isar2_el1",
"id_aa64pfr0_el1", "id_aa64mmfr1_el1", "id_aa64dfr0_el1", "id_aa64zfr0_el1",
"id_aa64pfr1_el1", "id_aa64mmfr2_el1", "midr_el1", "mpidr_el1", "revidr_el1",
};


Expand Down Expand Up @@ -194,7 +196,10 @@ const reg_id_t dr_reg_fixer[] = { REG_NULL,
DR_REG_P12, DR_REG_P13, DR_REG_P14, DR_REG_P15,
DR_REG_FFR,

DR_REG_CNTVCT_EL0,
DR_REG_CNTVCT_EL0, DR_REG_ID_AA64ISAR0_EL1, DR_REG_ID_AA64ISAR1_EL1,
DR_REG_ID_AA64ISAR2_EL1, DR_REG_ID_AA64PFR0_EL1, DR_REG_ID_AA64MMFR1_EL1,
DR_REG_ID_AA64DFR0_EL1, DR_REG_ID_AA64ZFR0_EL1, DR_REG_ID_AA64PFR1_EL1,
DR_REG_ID_AA64MMFR2_EL1, DR_REG_MIDR_EL1, DR_REG_MPIDR_EL1, DR_REG_REVIDR_EL1,
};

/* Maps real ISA registers to their corresponding virtual DR_ISA_REGDEPS register.
Expand Down Expand Up @@ -366,6 +371,18 @@ const reg_id_t d_r_reg_id_to_virtual[] = {
DR_REG_V195, /* DR_REG_FFR */

DR_REG_V196, /* DR_REG_CNTVCT_EL0 */
DR_REG_V197, /* DR_REG_ID_AA64ISAR0_EL1 */
DR_REG_V198, /* DR_REG_ID_AA64ISAR1_EL1 */
DR_REG_V199, /* DR_REG_ID_AA64ISAR2_EL1 */
DR_REG_V200, /* DR_REG_ID_AA64PFR0_EL1 */
DR_REG_V201, /* DR_REG_ID_AA64MMFR1_EL1 */
DR_REG_V202, /* DR_REG_ID_AA64DFR0_EL1 */
DR_REG_V203, /* DR_REG_ID_AA64ZFR0_EL1 */
DR_REG_V204, /* DR_REG_ID_AA64PFR1_EL1 */
DR_REG_V205, /* DR_REG_ID_AA64MMFR2_EL1 */
DR_REG_V206, /* DR_REG_MIDR_EL1 */
DR_REG_V207, /* DR_REG_MPIDR_EL1 */
DR_REG_V208, /* DR_REG_REVIDR_EL1 */
};
/* clang-format on */

Expand Down
18 changes: 15 additions & 3 deletions core/ir/opnd_api.h
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Original file line number Diff line number Diff line change
Expand Up @@ -1044,7 +1044,19 @@ enum {

# ifdef AARCH64
/* AArch64 Counter/Timer Register(s) */
DR_REG_CNTVCT_EL0, /**< Virtual Timer Count Register, EL0. */
DR_REG_CNTVCT_EL0, /**< Virtual Timer Count Register, EL0. */
DR_REG_ID_AA64ISAR0_EL1, /**< The "id_aa64isar0_el1" register. */
DR_REG_ID_AA64ISAR1_EL1, /**< The "id_aa64isar1_el1" register. */
DR_REG_ID_AA64ISAR2_EL1, /**< The "id_aa64isar2_el1" register. */
DR_REG_ID_AA64PFR0_EL1, /**< The "id_aa64pfr0_el1" register. */
DR_REG_ID_AA64MMFR1_EL1, /**< The "id_aa64mmfr1_el1" register. */
DR_REG_ID_AA64DFR0_EL1, /**< The "id_aa64dfr0_el1" register. */
DR_REG_ID_AA64ZFR0_EL1, /**< The "id_aa64zfr0_el1" register. */
DR_REG_ID_AA64PFR1_EL1, /**< The "id_aa64pfr1_el1" register. */
DR_REG_ID_AA64MMFR2_EL1, /**< The "id_aa64mmfr2_el1" register. */
DR_REG_MIDR_EL1, /**< The "midr_el1" register. */
DR_REG_MPIDR_EL1, /**< The "mpidr_el1" register. */
DR_REG_REVIDR_EL1, /**< The "revidr_el1" register. */
# endif

/* Aliases below here: */
Expand Down Expand Up @@ -1105,8 +1117,8 @@ enum {
DR_REG_CP15_C13_3 = DR_REG_TPIDRURO, /**< User Read-Only Thread ID Register */

# ifdef AARCH64
DR_REG_LAST_VALID_ENUM = DR_REG_CNTVCT_EL0, /**< Last valid register enum */
DR_REG_LAST_ENUM = DR_REG_CNTVCT_EL0, /**< Last value of register enums */
DR_REG_LAST_VALID_ENUM = DR_REG_REVIDR_EL1, /**< Last valid register enum */
DR_REG_LAST_ENUM = DR_REG_REVIDR_EL1, /**< Last value of register enums */
# else
DR_REG_LAST_VALID_ENUM = DR_REG_TPIDRURO, /**< Last valid register enum */
DR_REG_LAST_ENUM = DR_REG_TPIDRURO, /**< Last value of register enums */
Expand Down
2 changes: 1 addition & 1 deletion core/ir/opnd_shared.c
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Original file line number Diff line number Diff line change
Expand Up @@ -2780,7 +2780,7 @@ reg_get_size(reg_id_t reg)
}
if ((reg >= DR_REG_P0 && reg <= DR_REG_P15) || reg == DR_REG_FFR)
return OPSZ_SVE_PREDLEN_BYTES;
if (reg == DR_REG_CNTVCT_EL0)
if (reg >= DR_REG_CNTVCT_EL0 && reg <= DR_REG_REVIDR_EL1)
return OPSZ_8;
if (reg >= DR_REG_NZCV && reg <= DR_REG_FPSR)
return OPSZ_8;
Expand Down
12 changes: 12 additions & 0 deletions suite/tests/api/dis-a64.txt
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Expand Up @@ -31729,6 +31729,18 @@ d53beffd : mrs x29, pmccfiltr_el0 : mrs %pmccfiltr_el0 ->
d53c431d : mrs x29, spsr_irq : mrs %spsr_irq -> %x29
d53c433d : mrs x29, spsr_abt : mrs %spsr_abt -> %x29
d53c437e : mrs x30, spsr_fiq : mrs %spsr_fiq -> %x30
d5380600 : mrs x0, id_aa64isar0_el1 : mrs %id_aa64isar0_el1 -> %x0
d5380620 : mrs x0, id_aa64isar1_el1 : mrs %id_aa64isar1_el1 -> %x0
d5380640 : mrs x0, id_aa64isar2_el1 : mrs %id_aa64isar2_el1 -> %x0
d5380400 : mrs x0, id_aa64pfr0_el1 : mrs %id_aa64pfr0_el1 -> %x0
d5380720 : mrs x0, id_aa64mmfr1_el1 : mrs %id_aa64mmfr1_el1 -> %x0
d5380500 : mrs x0, id_aa64dfr0_el1 : mrs %id_aa64dfr0_el1 -> %x0
d5380480 : mrs x0, id_aa64zfr0_el1 : mrs %id_aa64zfr0_el1 -> %x0
d5380420 : mrs x0, id_aa64pfr1_el1 : mrs %id_aa64pfr1_el1 -> %x0
d5380740 : mrs x0, id_aa64mmfr2_el1 : mrs %id_aa64mmfr2_el1 -> %x0
d5380000 : mrs x0, midr_el1 : mrs %midr_el1 -> %x0
d53800a0 : mrs x0, mpidr_el1 : mrs %mpidr_el1 -> %x0
d53800c0 : mrs x0, revidr_el1 : mrs %revidr_el1 -> %x0

# MSR <cond>, #<imm> (MSR-I-SI_system)
d50040bf : msr SPSel, #0x0 : msr %spsel $0x00
Expand Down
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