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Various board updates for Netduino 3 Wifi (nanoframework#656)
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@piwi1263 @josesimoes
piwi1263 authored and josesimoes committed Mar 29, 2018
1 parent 2a53b3f commit 42b08d1
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Showing 5 changed files with 104 additions and 22 deletions.
7 changes: 6 additions & 1 deletion targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/CMakeLists.txt
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Expand Up @@ -55,6 +55,11 @@ if(API_Windows.Devices.SerialCommunication)
list(APPEND API_RELATED_TARGET_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_windows_devices_serialcommunication_config.cpp")
endif()

# Windows.Devices.Adc
if(API_Windows.Devices.Adc)
list(APPEND API_RELATED_TARGET_SOURCES "${CMAKE_CURRENT_SOURCE_DIR}/target_windows_devices_adc_config.cpp")
endif()

#######################################

add_subdirectory("common")
Expand Down Expand Up @@ -207,7 +212,7 @@ if(HEX2DFU_TOOL_AVAILABLE)
NF_GENERATE_DFU_PACKAGE(
${PROJECT_SOURCE_DIR}/build/${NANOBOOTER_PROJECT_NAME}.bin 08000000
${PROJECT_SOURCE_DIR}/build/${NANOCLR_PROJECT_NAME}.bin 08008000
${PROJECT_SOURCE_DIR}/build/nanobooter-nanoclr.dfu
${PROJECT_SOURCE_DIR}/build/nanoframework-4-netduino3wifi.dfu
)

endif()
30 changes: 15 additions & 15 deletions targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/board.h
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Original file line number Diff line number Diff line change
Expand Up @@ -294,12 +294,12 @@
* PB7 - I2C1_SDA
* PB8 - D5
* PB9 - D6
* PB10 - D10
* PB10 - D10 (=SPI2_SS)
* PB11 - MICROSD_INS
* PB12 - D4
* PB13 - D13
* PB14 - D12
* PB15 - D11
* PB13 - D13 (=SPI2_SCK)
* PB14 - D12 (=SPI2_MISO)
* PB15 - D11 (=SPI2_MOSI)
*/
#define VAL_GPIOB_MODER (PIN_MODE_OUTPUT(GPIOB_MICROSD_CS) | \
PIN_MODE_OUTPUT(GPIOB_MICROSD_CTRL) | \
Expand All @@ -311,12 +311,12 @@
PIN_MODE_ALTERNATE(GPIOB_I2C1_SDA) | \
PIN_MODE_INPUT(GPIOB_D5) | \
PIN_MODE_INPUT(GPIOB_D6) | \
PIN_MODE_INPUT(GPIOB_D10) | \
PIN_MODE_OUTPUT(GPIOB_D10) | \
PIN_MODE_INPUT(GPIOB_MICROSD_INS) | \
PIN_MODE_INPUT(GPIOB_D4) | \
PIN_MODE_INPUT(GPIOB_D13) | \
PIN_MODE_INPUT(GPIOB_D12) | \
PIN_MODE_INPUT(GPIOB_D11))
PIN_MODE_ALTERNATE(GPIOB_D13) | \
PIN_MODE_ALTERNATE(GPIOB_D12) | \
PIN_MODE_ALTERNATE(GPIOB_D11))
#define VAL_GPIOB_OTYPER (PIN_OTYPE_PUSHPULL(GPIOB_MICROSD_CS) | \
PIN_OTYPE_PUSHPULL(GPIOB_MICROSD_CTRL) | \
PIN_OTYPE_PUSHPULL(GPIOB_BOOT1) | \
Expand Down Expand Up @@ -394,9 +394,9 @@
PIN_AFIO_AF(GPIOB_D10, 0U) | \
PIN_AFIO_AF(GPIOB_MICROSD_INS, 0U) | \
PIN_AFIO_AF(GPIOB_D4, 0U) | \
PIN_AFIO_AF(GPIOB_D13, 0U) | \
PIN_AFIO_AF(GPIOB_D12, 0U) | \
PIN_AFIO_AF(GPIOB_D11, 0U))
PIN_AFIO_AF(GPIOB_D13, 5U) | \
PIN_AFIO_AF(GPIOB_D12, 5U) | \
PIN_AFIO_AF(GPIOB_D11, 5U))

/*
* GPIOC setup:
Expand All @@ -407,8 +407,8 @@
* PC3 - A3
* PC4 - A4
* PC5 - A5
* PC6 - D1
* PC7 - D0
* PC6 - USART6_TX_D1
* PC7 - USART6_RX_D0
* PC8 - CC_CS
* PC9 - LINK_LED
* PC10 - SPI3_CLK
Expand All @@ -424,8 +424,8 @@
PIN_MODE_ANALOG(GPIOC_A3) | \
PIN_MODE_ANALOG(GPIOC_A4) | \
PIN_MODE_ANALOG(GPIOC_A5) | \
PIN_MODE_INPUT(GPIOC_D1) | \
PIN_MODE_INPUT(GPIOC_D0) | \
PIN_MODE_ALTERNATE(GPIOC_D1) | \
PIN_MODE_ALTERNATE(GPIOC_D0) | \
PIN_MODE_OUTPUT(GPIOC_CC_CS) | \
PIN_MODE_OUTPUT(GPIOC_LINK_LED) | \
PIN_MODE_ALTERNATE(GPIOC_SPI3_CLK) | \
Expand Down
12 changes: 6 additions & 6 deletions targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/nanoCLR/mcuconf.h
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Original file line number Diff line number Diff line change
Expand Up @@ -59,9 +59,9 @@
* ADC driver system settings.
*/
#define STM32_ADC_ADCPRE ADC_CCR_ADCPRE_DIV4
#define STM32_ADC_USE_ADC1 FALSE
#define STM32_ADC_USE_ADC2 FALSE
#define STM32_ADC_USE_ADC3 FALSE
#define STM32_ADC_USE_ADC1 TRUE
#define STM32_ADC_USE_ADC2 TRUE
#define STM32_ADC_USE_ADC3 TRUE
#define STM32_ADC_ADC1_DMA_STREAM STM32_DMA_STREAM_ID(2, 4)
#define STM32_ADC_ADC2_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_ADC_ADC3_DMA_STREAM STM32_DMA_STREAM_ID(2, 1)
Expand Down Expand Up @@ -259,12 +259,12 @@
* SPI driver system settings.
*/
#define STM32_SPI_USE_SPI1 TRUE
#define STM32_SPI_USE_SPI2 FALSE
#define STM32_SPI_USE_SPI2 TRUE
#define STM32_SPI_USE_SPI3 TRUE
#define STM32_SPI_USE_SPI4 TRUE
#define STM32_SPI_SPI1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
#define STM32_SPI_SPI1_TX_DMA_STREAM STM32_DMA_STREAM_ID(2, 3)
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(0, 0) //1,3
#define STM32_SPI_SPI2_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 3)
#define STM32_SPI_SPI2_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 4)
#define STM32_SPI_SPI3_RX_DMA_STREAM STM32_DMA_STREAM_ID(1, 2)
#define STM32_SPI_SPI3_TX_DMA_STREAM STM32_DMA_STREAM_ID(1, 5)
Expand Down Expand Up @@ -294,7 +294,7 @@
#define STM32_UART_USE_USART3 TRUE
#define STM32_UART_USE_UART4 FALSE
#define STM32_UART_USE_UART5 FALSE
#define STM32_UART_USE_USART6 FALSE
#define STM32_UART_USE_USART6 TRUE
#define STM32_UART_USE_UART7 FALSE
#define STM32_UART_USE_UART8 FALSE
#define STM32_UART_USART1_RX_DMA_STREAM STM32_DMA_STREAM_ID(2, 2)
Expand Down
42 changes: 42 additions & 0 deletions targets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_adc_config.cpp
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@@ -0,0 +1,42 @@
//
// Copyright (c) 2018 The nanoFramework project contributors
// See LICENSE file in the project root for full license information.
//

#include "win_dev_adc_native.h"

//////////
// ADC1 //
//////////

const NF_PAL_ADC_PORT_PIN_CHANNEL Adc1PortPinConfig[] = {
{GPIOC, 0, ADC_CHANNEL_IN10},
{GPIOC, 1, ADC_CHANNEL_IN11},
{NULL, NULL, ADC_CHANNEL_SENSOR},
{NULL, NULL, ADC_CHANNEL_VREFINT},
{NULL, NULL, ADC_CHANNEL_VBAT},
};

const int Adc1ChannelCount = ARRAYSIZE(Adc1PortPinConfig);

//////////
// ADC2 //
//////////

const NF_PAL_ADC_PORT_PIN_CHANNEL Adc2PortPinConfig[] = {
{GPIOC, 2, ADC_CHANNEL_IN14},
{GPIOC, 3, ADC_CHANNEL_IN15},
};

const int Adc2ChannelCount = ARRAYSIZE(Adc2PortPinConfig);

//////////
// ADC3 //
//////////

const NF_PAL_ADC_PORT_PIN_CHANNEL Adc3PortPinConfig[] = {
{GPIOC, 4, ADC_CHANNEL_IN12},
{GPIOC, 5, ADC_CHANNEL_IN13},
};

const int Adc3ChannelCount = ARRAYSIZE(Adc3PortPinConfig);
35 changes: 35 additions & 0 deletions ...ets/CMSIS-OS/ChibiOS/NETDUINO3_WIFI/target_windows_devices_serialcommunication_config.cpp
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Original file line number Diff line number Diff line change
Expand Up @@ -41,3 +41,38 @@ UART_INIT(3, UART3_TX_SIZE, UART3_RX_SIZE)
// un-initialization for UART3
UART_UNINIT(3)

///////////
// UART6 //
///////////

// pin configuration for UART6
// port for TX pin is: GPIOC
// port for RX pin is: GPIOC
// TX pin: is GPIOC_6
// RX pin: is GPIOC_7
// GPIO alternate pin function is 7 (see "Table 12. STM32F427xx and STM32F429xx alternate function mapping" in STM32F427xx and STM32F429xx datasheet)
UART_CONFIG_PINS(6, GPIOC, GPIOC, 6, 7, 8)

// buffers size
// tx buffer size: 256 bytes
#define UART6_TX_SIZE 256
// rx buffer size: 256 bytes
#define UART6_RX_SIZE 256

// buffers
// buffers that are R/W by DMA are recommended to be aligned with 32 bytes cache page size boundary
// because of issues with cache coherency and DMA (this is particularly important with Cortex-M7 because of cache)
#if defined(__GNUC__)
__attribute__((aligned (32)))
#endif
uint8_t Uart6_TxBuffer[UART6_TX_SIZE];
#if defined(__GNUC__)
__attribute__((aligned (32)))
#endif
uint8_t Uart6_RxBuffer[UART6_RX_SIZE];

// initialization for UART6
UART_INIT(6, UART6_TX_SIZE, UART6_RX_SIZE)

// un-initialization for UART6
UART_UNINIT(6)

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