sys-DFF-ld-rst-block: updated

FPGAwars · Oct 14, 2023 · 2fe5766 · 2fe5766
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diff --git a/blocks/DFFs/Block/Sys-DFF-ld-rst.ice b/blocks/DFFs/Block/Sys-DFF-ld-rst.ice
@@ -1,9 +1,9 @@
 {
  "version": "1.2",
  "package": {
- "name": "sys-DFF-ld-rst",
- "version": "2.5",
- "description": "Sys-DFF-ld-rst. System - D Flip-flop. Capture data every system clock cycle. from input si. If load is active, the data is captured from the d input. Reset input",
+ "name": "sys-DFF-ld-rst-block",
+ "version": "3",
+ "description": "Sys-DFF-ld-rst. System - D Flip-flop. Capture data every system clock cycle. from input si. If load is active, the data is captured from the d input. Reset input. Block implementation",
  "author": "Juan González-Gómez (Obijuan)",
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@@ -51,14 +51,6 @@
  "type": "basic.input",
  "data": {
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- "virtual": true,
- "pins": [
- {
- "index": "0",
- "name": "NULL",
- "value": "NULL"
- }
- ],
  "clock": false
  },
  "position": {
@@ -71,15 +63,7 @@
  "type": "basic.inputLabel",
  "data": {
  "name": "rst",
- "blockColor": "red",
- "virtual": true,
- "pins": [
- {
- "index": "0",
- "name": "NULL",
- "value": "NULL"
- }
- ]
+ "blockColor": "red"
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@@ -220,15 +204,7 @@
  "type": "basic.outputLabel",
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- "blockColor": "red",
- "virtual": true,
- "pins": [
- {
- "index": "0",
- "name": "NULL",
- "value": "NULL"
- }
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+ "blockColor": "red"
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@@ -423,18 +399,6 @@
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+ "height": 64
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@@ -557,13 +533,13 @@
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- "block": "3e66b384-c29b-4edf-9831-6e5140a89691",
+ "block": "2a8bebbd-73c4-4142-b5a4-80311a25952b",
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- "block": "3e66b384-c29b-4edf-9831-6e5140a89691",
+ "block": "2a8bebbd-73c4-4142-b5a4-80311a25952b",
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@@ -577,7 +553,7 @@
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- "block": "3e66b384-c29b-4edf-9831-6e5140a89691",
+ "block": "2a8bebbd-73c4-4142-b5a4-80311a25952b",
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@@ -597,7 +573,7 @@
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+ "block": "2a8bebbd-73c4-4142-b5a4-80311a25952b",
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@@ -780,10 +756,99 @@
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- "dfa7edc9373492388c38c768173e06aea82860d6": {
+ "6b14d5741f7e62a08c61190175d6447b05954bbd": {
+ "package": {
+ "name": "1-bit-gen-constant",
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+ "author": "Juan Gonzalez-Gomez (Obijuan)",
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+ "design": {
+ "graph": {
+ "blocks": [
+ {
+ "id": "5d443143-4aca-4d4f-ba40-2b88451b86d3",
+ "type": "basic.output",
+ "data": {
+ "name": ""
+ },
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+ "y": 248
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+ {
+ "id": "7dbe7521-0f9f-43ee-ab0c-0439e2c20bc2",
+ "type": "basic.code",
+ "data": {
+ "code": "assign k = VALUE;",
+ "params": [
+ {
+ "name": "VALUE"
+ }
+ ],
+ "ports": {
+ "in": [],
+ "out": [
+ {
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+ }
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+ "port": "k"
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+ "port": "in"
+ }
+ }
+ ]
+ }
+ }
+ },
+ "58ed2b5c7e33e2f215ccba6c101d9ea4ff60f284": {
  "package": {
  "name": "sys-DFF-verilog",
- "version": "2.3",
+ "version": "3",
  "description": "System - D Flip-flop. Capture data every system clock cycle. Verilog implementation",
  "author": "Juan González-Gómez (Obijuan)",
  "image": "%3Csvg%20width=%22196.313%22%20height=%22216.83%22%20viewBox=%220%200%2051.941051%2057.369679%22%20xmlns=%22http://www.w3.org/2000/svg%22%3E%3Cg%20transform=%22translate(-52.22%20-48.028)%22%3E%3Crect%20width=%2224.412%22%20height=%2213.185%22%20x=%2279.352%22%20y=%2253.67%22%20ry=%222.247%22%20fill=%22#fff%22%20stroke=%22#000%22%20stroke-width=%22.794%22%20stroke-linecap=%22round%22/%3E%3Cg%20stroke=%22#000%22%20stroke-width=%221.442%22%20stroke-linecap=%22round%22%20stroke-linejoin=%22round%22%3E%3Cpath%20d=%22M77.902%2088.18l13.607%2016.672-6.918-20.534%22%20fill=%22#ccc%22%20stroke-width=%221.0924880399999999%22/%3E%3Cpath%20d=%22M70.517%2080.116l-9.232-19.613-6.45%203.725-2.07-3.584%2020.905-12.07%202.07%203.584-6.093%203.518%2012.03%2018.222s5.4-2.025%208.536.74c3.136%202.766%202.52%204.92%202.887%204.773L69.412%2093.049s-2.848-3.696-2.16-6.796c.687-3.1%203.265-6.137%203.265-6.137z%22%20fill=%22red%22%20stroke-width=%221.0924880399999999%22/%3E%3C/g%3E%3Ctext%20style=%22line-height:1.25%22%20x=%2281.296%22%20y=%2263.239%22%20font-weight=%22400%22%20font-size=%2210.583%22%20font-family=%22sans-serif%22%20fill=%22#00f%22%20stroke-width=%22.265%22%3E%3Ctspan%20style=%22-inkscape-font-specification:'sans-serif%20Bold'%22%20x=%2281.296%22%20y=%2263.239%22%20font-weight=%22700%22%3ESys%3C/tspan%3E%3C/text%3E%3C/g%3E%3C/svg%3E"
@@ -811,7 +876,7 @@
  },
  "position": {
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- "y": 160
+ "y": 184
  }
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@@ -822,7 +887,7 @@
  },
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- "y": 224
+ "y": 232
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@@ -834,7 +899,7 @@
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+ "y": 280
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  {
@@ -854,7 +919,7 @@
  "id": "bdc170f0-4468-4137-bd79-4624c9cadf2b",
  "type": "basic.code",
  "data": {
- "code": "//-- Initial value\nreg q = INI;\n\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n q <= d;",
+ "code": "//-- Initial value\nreg qi = INI;\n\n//-- Capture the input data \n//-- on the rising edge of \n//-- the system clock\nalways @(posedge clk)\n qi <= d;\n \n//-- Connect the register with the\n//-- output\nassign q = qi;",
  "params": [
  {
  "name": "INI"
@@ -881,8 +946,8 @@
  "y": 168
  },
  "size": {
- "width": 344,
- "height": 176
+ "width": 352,
+ "height": 192
  }
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@@ -910,7 +975,7 @@
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+ "y": 160
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@@ -926,7 +991,7 @@
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+ "y": 256
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@@ -1026,95 +1091,6 @@
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  }
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- "package": {
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 }