Merge branch 'main' of https://github.com/FPGAwars/iceFF

FPGAwars · Oct 14, 2023 · 6335ccc · 6335ccc
2 parents d52fc69 + 9190f56
commit 6335ccc
Showing 1 changed file with 1 addition and 1 deletion.
diff --git a/locale/translation.js b/locale/translation.js
@@ -59,7 +59,7 @@ gettext('Sys-DFF-ld-rst');
 gettext('Sys-DFF-ld-rst. System - D Flip-flop. Capture data every system clock cycle. from input si. If load is active, the data is captured from the d input. Reset input');
 gettext('2-to-1 Multplexer (1-bit channels). Verilog implementation');
 gettext('Sys-DFF-ld');
-gettext('Sys-DFF-ld. System - D Flip-flop. Capture data every system clock cycle. from input si. If load is active, the data is captured from the d input');
+gettext('Sys-DFF-ld. System - D Flip-flop. Capture data every system clock cycle. from input si. If load is active, the data is captured from the d input. Block implementation');
 gettext('Sys-DFF-rst');
 gettext('Sys-DFF-rst: D Flip flop with reset input. When rst=1, the DFF is set to it initial value. Block implementation');
 gettext('Reset input: Active high \nWhen rst=1, the DFF is set to \nits initial value');