Add configUSE_TASK_FPU_SUPPORT to AARCH64 port #1048
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NEON SIMD is required by standard AARCH64 and its registers are frequently utilized by standard functions such as memcpy(). This means that even simple tasks that do not use any floating point arithmetics may still alter the contents of the FPU registers. For this reason it makes sense to add support for configUSE_TASK_FPU_SUPPORT to be able to enforce FPU register saving and restoring globally. The implementation was largely adopted from the ARM_CA9 port. However, the FPU registers must be placed on the stack before the critical nesting count to match the AARCH64 portASM.S.
n9wxu
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May 7, 2024
chinglee-iot
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May 7, 2024
aggarg
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May 7, 2024
Signed-off-by: Gaurav Aggarwal <aggarg@amazon.com>
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aggarg
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May 8, 2024
shubnil
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@StefanBalt Thank you for your contribution. |
schilkp
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* Add configUSE_TASK_FPU_SUPPORT to AARCH64 port NEON SIMD is required by standard AARCH64 and its registers are frequently utilized by standard functions such as memcpy(). This means that even simple tasks that do not use any floating point arithmetics may still alter the contents of the FPU registers. For this reason it makes sense to add support for configUSE_TASK_FPU_SUPPORT to be able to enforce FPU register saving and restoring globally. The implementation was largely adopted from the ARM_CA9 port. However, the FPU registers must be placed on the stack before the critical nesting count to match the AARCH64 portASM.S.
MinghuanLian
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Nov 28, 2024
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (FreeRTOS#1048)" [2] FreeRTOS#1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
asellaminxp
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Nov 28, 2024
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (FreeRTOS#1048)" [2] FreeRTOS#1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
asellaminxp
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Jan 22, 2025
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (FreeRTOS#1048)" [2] FreeRTOS#1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
asellaminxp
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Jan 22, 2025
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (FreeRTOS#1048)" [2] FreeRTOS#1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
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archigup
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Jan 23, 2025
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (#1048)" [2] #1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
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Description
NEON SIMD is required by standard AARCH64 and its registers are frequently utilized by standard functions such as memcpy(). This means that even simple tasks that do not use any floating point arithmetics may still alter the contents of the FPU registers.
For this reason it makes sense to add support for configUSE_TASK_FPU_SUPPORT to be able to enforce FPU register saving and restoring globally.
Without configUSE_TASK_FPU_SUPPORT it is not possible to enforce this for some library tasks.
This pull request partially fixes this issue:
https://forums.freertos.org/t/zynq-ultrascale-mpsoc-task-floating-point-corruption/9121
For a full fix
portASM.Salso needs to be adapted to save/restore all FPU registers at interrupt entry/exit.Maybe I will find time to contribute this in another pull request.
Checklist:
No regression in existing tests.(stack consumption and timing will get worse)Related Issue
My colleague did already something similar for the ARM Cortex R5 port: GH-584
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