Add FPU Context Handling for ARM_AARCH64_SRE port #1229
Conversation
This is a direct backport of upstream commit [1] for aarch64 (legacy operation port) done under [2] The same code can be applied on the aarch SRE port to be able to enable FPU context saving on all tasks context switch to mitigate GCC optimization to use SIMD registers for copy. [1] "55eceb22: Add configUSE_TASK_FPU_SUPPORT to AARCH64 port (FreeRTOS#1048)" [2] FreeRTOS#1048 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
…the fpu saved context FPSR and FPCR are two 64-bits registers where only the lower 32 bits are defined. Save them when doing context switch with FPU context saving enabled. Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
The application writer needs to name their IRQ handler as: 1. vApplicationIRQHandler if the IRQ handler does not use FPU registers. 2. vApplicationFPUSafeIRQHandler is the IRQ handler uses FPU registers. When the application uses vApplicationFPUSafeIRQHandler, a default implementation of vApplicationIRQHandler is used which stores FPU registers and then calls vApplicationFPUSafeIRQHandler. Note that recent versions of GCC may use FP/SIMD registers to optimize 16-bytes copy and especially when using va_start()/va_arg() functions (e.g printing some thing in IRQ handlers may trigger usage of FPU registers) This implementation is heavily inspired by both the ARM_CA9 port and the ARM_CRx_No_GIC port done in [1] [1] FreeRTOS#1113 Signed-off-by: Marouen Ghodhbane <marouen.ghodhbane@nxp.com>
|
asellaminxp
deleted the
upstream/aarch64_sre_add_fpu_context_save_support
branch
|
@asellaminxp I am trying to understand why we need to save FPCR and FPSR as part of the context -
The non SRE port does not save FPCR and FPSR as part of the context either. Would you please help me understand why we need to save these registers as part of the context. |
|
Hi @aggarg The save/restore for the status and control registers was more of a precaution (and by comparing to what other implementations are doing) than a targeted fix (As a general rule of thumb, we tend to save the control and status registers as part of the context). CC @asellaminxp |
|
Thank you for your response @GhMarwen! At the moment, it is inconsistent between SRE and non-SRE ports for AArch64. I'd prefer to keep it same in both the ports. I have reached out to Arm to ask about their suggestion and based on what I hear from them, we'll make both the ports same. Will keep you posted. |
|
FPSR and FPCR are both state controllable by the running process (EL0 code). Hence, they need to be saved and restored by context switches in exactly the same way all the general purpose registers are. This applies to both ARM_AARCH64 and ARM_ARRCH64_SRE ports, since the changes were already done to ARM_AARCH64_SRE port as part of this PR, then we just need to apply the same changes for the ARM_ARRCH64 port as well. Thanks |
Add FPU Context Handling for ARM_AARCH64_SRE port.
Description
Test Steps
Tested on our example applications NXP/harpoon-apps, which are demo applications running on Cortex-A using the jailhouse hypervisor with Linux running and FreeRTOS as a guest OS.
Checklist:
Related Issue
By submitting this pull request, I confirm that you can use, modify, copy, and redistribute this contribution, under the terms of your choice.