Merge pull request #379 from GSI-CS-CO/fallout_pexp_pps

Fallout pexp pps

Makefile

@@ -40,6 +40,7 @@ CHECK_PMC              = ./syn/gsi_pmc/control/pci_pmc
 CHECK_MICROTCA         = ./syn/gsi_microtca/control/microtca_control
 CHECK_PEXP             = ./syn/gsi_pexp/control/pexp_control
 CHECK_PEXP_SDR         = ./syn/gsi_pexp/sdr/pexp_control_sdr
+CHECK_PEXP_PPS         = ./syn/gsi_pexp/pps/pexp_pps
 CHECK_SCU4             = ./syn/gsi_scu/control4/scu_control
 CHECK_FTM4             = ./syn/gsi_scu/ftm4/ftm4
 CHECK_FTM4DP           = ./syn/gsi_scu/ftm4dp/ftm4dp
@@ -62,6 +63,7 @@ PATH_PMC               = syn/gsi_pmc/control
 PATH_MICROTCA          = syn/gsi_microtca/control
 PATH_PEXP              = syn/gsi_pexp/control
 PATH_PEXP_SDR          = syn/gsi_pexp/sdr
+PATH_PEXP_PPS          = syn/gsi_pexp/pps
 PATH_SCU4              = syn/gsi_scu/control4
 PATH_FTM4              = syn/gsi_scu/ftm4
 PATH_FTM4DP            = syn/gsi_scu/ftm4dp
@@ -535,6 +537,18 @@ pexp-sdr-sort:
 pexp-sdr-check:
 	$(call check_timing, $(CHECK_PEXP_SDR))
 
+pexp-pps:	firmware
+	$(MAKE) -C $(PATH_PEXP_PPS) all
+
+pexp-pps-clean::
+	$(MAKE) -C $(PATH_PEXP_PPS) clean
+
+pexp-pps-sort:
+	$(call sort_file, $(CHECK_PEXP_PPS))
+
+pexp-pps-check:
+	$(call check_timing, $(CHECK_PEXP_PPS))
+
 avsoc:		firmware
 	$(MAKE) -C syn/gsi_avsoc/av_rocket_board all
 

modules/enc_err_counter/readme.md

@@ -1,21 +1,31 @@
 # PHY Encoder Error Counter
 
-> [!IMPORTANT]  
-> In this branch the ECA and the PCI-E module for the pexarria5 have been turned off for quicker build times for testing
+[!IMPORTANT]
+This module counts the pulses coming from the PHY enc_err output and transfers them to the system clock domain. There they can be read via Wishbone.
 
-This module counts the pulses coming from the PHY enc_err output and transfers them to the system clock domain. There they can be read via Wishbone.   
-- `0x00` Error Counter 1  
-- `0x04` Error Counter 2 (auxiliary)  
-- `0x08` Overflow Flag 1  
-- `0x0C` Overflow Flag 2
+| Address | Meaning |
+| ------- | ------- |
+| 0x00    | Error Counter 1 |
+| 0x04    | Error Counter 2 (auxiliary) |
+| 0x08    | Overflow Flag 1 |
+| 0x0C    | Overflow Flag 2 (auxiliary) |
 
 ## Manual Counter Reset
-**Be sure to save or write down the error count before reset. The reset completely deletes the data**
-To reset a counter without a power cycle you can write a one into the counter address. The following write resets error counter one and it's overflow flag.  
-`eb-write <proto/host/port> 0xXXXXXX00/4 0x00000001`  
-
-The reset is a toggle. The counter won't rise as long as it is set. So the reset register has to be set to 0 again by:  
-`eb-write <proto/host/port> 0xXXXXXX00/4 0x00000000`
-
-## Clock Domain Crossing  
-The clock domain is crossed using grey code encoding and a sync register.
+
+**Be sure to save or write down the error count before reset. The reset completely deletes the data.**
+
+To reset a counter without a power cycle you can write a one into the counter address. The following write resets error counter one and it's overflow flag:
+
+```
+eb-write <proto/host/port> 0xXXXXXX00/4 0x00000001
+```
+
+The reset is a toggle. The counter won't rise as long as it is set. So the reset register has to be set to 0 again by:
+
+```
+eb-write <proto/host/port> 0xXXXXXX00/4 0x00000000
+```
+
+## Clock Domain Crossing
+
+The clock domain is crossed using gray code encoding and a sync register.

syn/gsi_pexp/pps/Makefile

@@ -0,0 +1,7 @@
+TARGET		= pexp_pps
+DEVICE		= 5AGXMA3D4
+FLASH		= EPCQ256
+SPI_LANES	= ASx4
+RAM_SIZE	= 131072
+
+include ../../build.mk

syn/gsi_pexp/pps/Manifest.py

@@ -0,0 +1,20 @@
+target = "altera"
+action = "synthesis"
+
+fetchto = "../../../ip_cores"
+
+syn_device = "5agxma3d4f"
+syn_grade = "i3"
+syn_package = "27"
+syn_top = "pexp_pps"
+syn_project = "pexp_pps"
+
+quartus_preflow = "pexp_pps.tcl"
+
+modules = {
+  "local" : [
+    "../../../top/gsi_pexp/pps",
+  ]
+}
+
+syn_tool = "quartus"

syn/gsi_pexp/pps/pexp_pps.qpf

@@ -0,0 +1 @@
+PROJECT_REVISION = "pexp_pps"

syn/gsi_pexp/pps/pexp_pps.tcl

@@ -0,0 +1,9 @@
+set platform "pexp_pps"
+source ../../autogen.tcl
+source ../../../modules/build_id/build_id.tcl
+source ../../../ip_cores/general-cores/platform/altera/networks/arria5.tcl
+source ../../../ip_cores/general-cores/platform/altera/wb_pcie/arria5.tcl
+source ../../../modules/pll/arria5/arria5_pll.tcl
+source ../../../ip_cores/wr-cores/platform/altera/wr_arria5_phy/wr_arria5_phy.tcl
+source ../../common/arria5_legacy_flash_patch.tcl
+source ../../common/arria5_serdes_lvds_patch.tcl

top/gsi_pexp/pps/Manifest.py

@@ -0,0 +1,11 @@
+files = [
+   "pexp_pps.vhd",
+   "../../common/arria5.sdc",
+   "ramsize_pkg.vhd"
+]
+
+modules = {
+  "local" : [
+    "../../..",
+  ]
+}