Feature blm aco

Makefile

@@ -471,6 +471,12 @@ ifa8:		firmware
 ifa8-clean::
 	$(MAKE) -C syn/gsi_ifa8 clean
 
+blm:		firmware
+	$(MAKE) -C syn/blm_aco all
+
+blm-clean::
+	$(MAKE) -C syn/blm_aco clean
+
 # #################################################################################################
 # LM32 firmware
 # #################################################################################################

top/blm_aco/BLM_Interlock_out.vhd

@@ -0,0 +1,123 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+
+entity BLM_Interlock_out is
+
+
+port (
+        CLK              : in std_logic;      -- Clock
+        nRST             : in std_logic;      -- Reset
+        out_mux_sel      : in std_logic_vector(15 downto 0);
+        UP_OVERFLOW      : in std_logic_vector(255 downto 0);
+        DOWN_OVERFLOW    : in std_logic_vector(255 downto 0);
+        gate_error       : in std_logic_vector(11 downto 0);
+        Interlock_IN     : in std_logic_vector(53 downto 0);
+        gate_out        : in std_logic_vector (11 downto 0);
+        INTL_Output      : out std_logic_vector(5 downto 0);
+        BLM_status_Reg : out t_IO_Reg_0_to_7_Array
+);
+end BLM_Interlock_out;
+
+architecture rtl of BLM_Interlock_out is
+
+      signal in_overflow: std_logic_vector(511 downto 0);
+      signal overflow: std_logic_vector(5 downto 0);
+      signal overflow_in: std_logic_vector (767 downto 0);
+      signal m: integer range 0 to 255 :=0;
+      signal overflow_cnt: std_logic_vector(6 downto 0);
+      constant ZERO_OVERFLOW:  std_logic_vector (in_overflow'range) := (others => '0');
+      signal gate_signal : std_logic_vector(11 downto 0);
+      signal no_overflow: std_logic;
+
+      component overflow_ram IS
+      PORT
+      (
+
+		    aclr		: IN STD_LOGIC  := '0';
+        clock		: IN STD_LOGIC  := '1';
+        data		: IN STD_LOGIC_VECTOR (5 DOWNTO 0);
+        rdaddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+        rden		: IN STD_LOGIC  := '1';
+        wraddress		: IN STD_LOGIC_VECTOR (6 DOWNTO 0);
+        wren		: IN STD_LOGIC  := '0';
+        q		: OUT STD_LOGIC_VECTOR (5 DOWNTO 0)
+      );
+
+      end component;
+
+      begin
+
+        mux_in_process:process (nRST, CLK)
+        begin
+        if not nRST='1' then 
+              in_overflow <=   (OTHERS =>  '0');   
+              overflow_in <= (OTHERS =>'0');
+              overflow_cnt <= (OTHERS =>'0');
+              no_overflow <='0';
+
+
+       elsif (CLK'EVENT AND CLK = '1') then  
+
+
+        in_overflow <= UP_OVERFLOW& DOWN_OVERFLOW;
+
+        if in_overflow = ZERO_OVERFLOW then
+          no_overflow <='1';
+        end if;
+
+
+        overflow_in(581 downto 0) <=  gate_error & Interlock_IN  & "0000" &in_overflow;  --2 x 6bit gate values, 9x6bit watchgdog interlock values + 86 x 6 bit values
+        overflow_in(767 downto 582) <= (others =>'0');
+
+
+        if out_mux_sel(8) ='1' then 
+           m <=0;
+
+        elsif out_mux_sel(9) ='1' then
+          m <= m + 1;
+          if m = 127 then      
+            m <= 0;
+          end if;
+
+        end if;
+
+        overflow_cnt <= std_logic_vector(to_unsigned(m,7));
+
+      end if;
+
+    end process;
+
+
+        overflow_ram_el: overflow_ram 
+
+        port map(
+
+          aclr	=> out_mux_sel(7),
+          clock	=> CLK,
+          data		=> overflow_in((6*m +5) downto (6*m)),
+          rdaddress	=> out_mux_sel(6 downto 0),
+          rden		=> out_mux_sel(9),
+          wraddress	=> overflow_cnt,
+          wren	=> out_mux_sel(8),
+          q		=> overflow
+        );
+
+        INTL_Output <= overflow;
+        gate_signal <= gate_out;
+     --------------------------------------------------------------------------------------------------
+     -----                         BLM_STATUS_REGISTERS               
+     --------------------------------------------------------------------------------------------------
+
+        BLM_status_reg(0)<=  '0'& out_mux_sel(6 downto 0)& '0'& no_overflow &  INTL_Output; -- out_mux_sel(6..0) readback, gate_overflow e input_overflow absence, BLM output
+        BLM_status_reg(1)<= "00"& gate_error(11 downto 6) & "00" & gate_error(5 downto 0);         -- gate error
+        BLM_status_reg(2)<= "00"& interlock_IN(11 downto 6) & "00" & Interlock_IN(5 downto 0);    -- interlock board 1 and board 2
+        BLM_status_reg(3)<= "00"& interlock_IN(23 downto 18) & "00" & Interlock_IN(17 downto 12); -- interlock board 3 and board 4
+        BLM_status_reg(4)<= "00" & interlock_IN(35 downto 30)&"00"& Interlock_IN(29 downto 24);   -- interlock board 5 and board 6
+        BLM_status_reg(5)<= "00"& interlock_IN(47 downto 42)&"00"& Interlock_IN(41 downto 36);    -- interlock board 7 and board 8
+        BLM_status_reg(6)<= "0000000000"& interlock_IN(53 downto 48);                             -- interlock board 9
+        BLM_status_reg(7) <= "00"& gate_signal(11 downto 6) & "00" & gate_signal(5 downto 0);
+
+
+end rtl;

top/blm_aco/BLM_counter_pool_el.vhd

@@ -0,0 +1,146 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+
+entity BLM_counter_pool_el is
+    generic (      
+        WIDTH        : integer := 30      -- Counter width
+
+    );
+    port (
+        CLK               : in std_logic;      -- Clock
+        nRST              : in std_logic;      -- Reset
+        gate_reset_ena    : in std_logic;
+        RESET             : in std_logic;      -- global reset
+        ENABLE            : in std_logic;      -- Enable count operation (gate signals)
+        pos_threshold     : in std_logic_vector(31 downto 0);
+        neg_threshold     : in std_logic_vector(31 downto 0);
+        in_counter        : in std_logic_vector(63 downto 0);
+        BLM_cnt_Reg     : in std_logic_vector(15 downto 0);  --bit 11..0
+        cnt    : out std_logic_vector (WIDTH-1 downto 0);    --  Counter register
+
+        UP_OVERFLOW       : out std_logic;     -- UP_Counter overflow for the input signals
+        DOWN_OVERFLOW     : out std_logic    -- DOWN_Counter overflow for the input signals
+
+    );
+end BLM_counter_pool_el;
+
+architecture rtl of BLM_counter_pool_el is
+
+signal cnt_enable: std_logic;
+signal cnt_up, cnt_down: std_logic;
+
+    component BLM_in_mux is
+        port (
+            CLK               : in std_logic;      -- Clock
+            nRST              : in std_logic;      -- Reset
+            mux_sel           : in std_logic_vector(11 downto 0);
+            in_mux            : in std_logic_vector(63 downto 0);
+            cnt_up            : out std_logic;     -- UP_Counter input 
+            cnt_down          : out std_logic    -- DOWN_Counter input  
+        );
+    end component BLM_in_mux;
+
+    component up_down_counter is
+        generic (
+
+            WIDTH        : integer := 30     -- Counter width
+
+        );
+        port (
+
+        CLK              : in std_logic;      -- Clock
+        nRST             : in std_logic;      -- Reset
+        CLEAR            : in std_logic;      -- Clear counter registers
+
+        ENABLE           : in std_logic;      -- Enable count operation
+        pos_threshold    : in integer;
+        neg_threshold    : in integer;
+        UP_IN            : in std_logic;      -- Load counter register up input
+        DOWN_IN          : in std_logic;      -- Load counter register down input
+        cnt_val    : out std_logic_vector (WIDTH-1 downto 0);    -- Counter register
+
+        UP_OVERFLOW      : out std_logic;     -- UP_Counter overflow
+        DOWN_OVERFLOW    : out std_logic      -- UP_Counter overflow
+        );
+    end component up_down_counter; 
+
+
+
+signal CLEAR: std_logic;
+
+begin
+
+
+ clear_and_cnt_enable_process: process (clk, nRST)
+   begin
+        if not nRST='1' then 
+
+
+           cnt_enable <='0';
+             CLEAR <='1';
+
+        elsif (clk'EVENT AND clk= '1') then 
+
+            if RESET ='1' then --counter reset
+
+                cnt_enable <='0';
+                CLEAR <='1';
+
+            --elsif ENABLE = '1' then 
+
+            else
+
+                cnt_enable <= ENABLE;
+                if  gate_reset_ena = '0' then
+                    CLEAR <='0';   
+                else 
+                    CLEAR <= ENABLE;
+                end if;
+
+            end if;
+        end if;
+end process;
+
+
+
+
+
+    in_multiplexer: BLM_in_mux 
+        port map(
+            CLK           => clk,    -- Clock
+            nRST          => nRST,      -- Reset
+            mux_sel       =>  BLM_cnt_Reg(11 downto 0),
+            in_mux        => in_counter,
+            cnt_up        => cnt_up,   -- UP_Counter input 
+            cnt_down      => cnt_down    -- DOWN_Counter input  
+        );
+
+
+
+    Counter_module: up_down_counter 
+     generic map
+        (   
+            WIDTH         => 30 --WIDTH   -- Counter width
+
+        )
+    port map
+        (   CLK           => clk,    -- Clock
+            nRST          => nRST,      -- Reset
+            CLEAR         => CLEAR,     -- Clear counter register
+            ENABLE        => cnt_enable,   -- Enable count operation
+
+            pos_threshold => to_integer(signed(pos_threshold)),
+            neg_threshold => to_integer(signed(neg_threshold)),
+            UP_IN         => cnt_up,   -- Load counter register up input
+            DOWN_IN       => cnt_down,  -- Load counter register down input
+            cnt_val   => cnt,
+
+
+            UP_OVERFLOW   => UP_OVERFLOW,    -- UP_Counter overflow 
+            DOWN_OVERFLOW => DOWN_OVERFLOW   -- UP_Counter overflow 
+        );
+
+
+end rtl;

top/blm_aco/BLM_ena_in_mux.vhd

@@ -0,0 +1,63 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+
+entity BLM_ena_in_mux is
+    port (
+        CLK               : in std_logic;      -- Clock
+        nRST              : in std_logic;      -- Reset
+        mux_sel           : in t_BLM_reg_Array;  -- I need only bit 15..12 of each BLM_in_sel_Reg register
+        in_mux            : in std_logic_vector(11 downto 0);
+        cnt_enable        : out std_logic_vector(127 downto 0)
+    );
+end BLM_ena_in_mux;
+
+architecture rtl of BLM_ena_in_mux is
+
+TYPE gate_sel_array is ARRAY (0 to 127) of INTEGER RANGE 0 to 15;
+signal gate_sel: gate_sel_array;
+signal uns_in: unsigned(11 downto 0);
+signal uns_enable: unsigned(127 downto 0);
+
+
+begin
+ uns_in <= unsigned(in_mux);            
+cnt_enable_proc: process (clk,nRST)
+begin
+    if not nRST='1' then 
+
+     gate_sel  <= (others => 0);
+     uns_enable <= (others =>'0');
+
+elsif (clk'EVENT AND clk= '1') then 
+
+for i in 0 to 127 loop
+
+    gate_sel(i) <=  to_integer(unsigned(mux_sel(i)(15 downto 12)));
+
+    case gate_sel(i) is
+
+        when 0  =>  uns_enable(i) <= uns_in(0);
+        when 1  =>  uns_enable(i) <= uns_in(1);
+        when 2  =>  uns_enable(i) <= uns_in(2);
+        when 3  =>  uns_enable(i) <= uns_in(3);
+        when 4  =>  uns_enable(i) <= uns_in(4);
+        when 5  =>  uns_enable(i) <= uns_in(5);
+        when 6  =>  uns_enable(i) <= uns_in(6);
+        when 7  =>  uns_enable(i) <= uns_in(7);
+        when 8  =>  uns_enable(i) <= uns_in(8);
+        when 9  =>  uns_enable(i) <= uns_in(9);
+        when 10 =>  uns_enable(i) <= uns_in(10);
+        when 11 =>  uns_enable(i) <= uns_in(11);
+        when others => NULL;
+
+    end case;
+end loop;
+
+end if;
+
+
+end process;
+cnt_enable <= std_logic_vector(uns_enable);
+end architecture;

top/blm_aco/BLM_gate_err_mux.vhd

@@ -0,0 +1,49 @@
+LIBRARY IEEE;
+USE IEEE.std_logic_1164.all;
+USE IEEE.numeric_std.all;
+use work.scu_diob_pkg.all;
+
+entity BLM_gate_err_mux is
+
+    port (
+        CLK             : in std_logic;      -- Clock
+        nRST            : in std_logic;      -- Reset
+        sel             : in t_BLM_12_to_6_mux_sel_array ;
+        in_s            : in std_logic_vector(11 downto 0);
+        out_s           : out std_logic_vector(5 downto 0)
+
+    );
+end BLM_gate_err_mux;
+
+architecture rtl of BLM_gate_err_mux is
+
+TYPE t_sel is array (0 to 5) of integer range 0 to 11;
+signal int_sel: t_sel;
+signal out_signal: std_logic_vector(5 downto 0);
+
+
+
+
+begin
+
+  proc_b: process (clk,nRST)
+    begin
+        if not nRST='1' then 
+             for i in 0 to 5 loop
+             	int_sel(i) <=0;
+             end loop;
+            out_signal <=( others =>'0');
+
+
+        elsif (clk'EVENT AND clk= '1') then 
+
+           for i in 0 to 5 loop
+             int_sel(i) <= to_integer(unsigned (sel(i)));
+             out_signal(i)<= in_s(int_sel(i));
+
+           end loop;
+
+        end if;
+        out_s <= out_signal;
+    end process;
+end architecture;