Implementando tratamento de instrucões de salto

Implementando instrucões de branch, e "preditor" branch taken
JN513 · Nov 6, 2024 · 6ec4a1f · 6ec4a1f
1 parent 777ff15
commit 6ec4a1f
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Showing 5 changed files with 63 additions and 6 deletions.
diff --git a/software/code/branch_test.S b/software/code/branch_test.S
@@ -0,0 +1,16 @@
+.text
+.global _start
+
+_start:
+    addi a1, zero, 10      # Carrega o primeiro número (10) em a1
+    addi a2, zero, 20      # Carrega o segundo número (20) em a2
+
+    beq a1, a1, equal
+
+    nop
+    nop
+    nop
+    nop
+
+equal:
+    li a5, 15
diff --git a/software/code/branch_test2.S b/software/code/branch_test2.S
@@ -0,0 +1,16 @@
+.text
+.global _start
+
+_start:
+    addi a1, zero, 10      # Carrega o primeiro número (10) em a1
+    addi a2, zero, 20      # Carrega o segundo número (20) em a2
+
+    beq a1, a2, equal
+
+    nop
+    nop
+    nop
+    nop
+
+equal:
+    li a5, 15
diff --git a/software/memory/branch_test.hex b/software/memory/branch_test.hex
@@ -0,0 +1,8 @@
+00a00593
+01400613
+00b58a63
+00000013
+00000013
+00000013
+00000013
+00f00793
diff --git a/software/memory/branch_test2.hex b/software/memory/branch_test2.hex
@@ -0,0 +1,8 @@
+00a00593
+01400613
+00c58a63
+00000013
+00000013
+00000013
+00000013
+00f00793
diff --git a/src/core/core.v b/src/core/core.v
@@ -67,20 +67,23 @@ wire [4:0] IFIDrs1, IFIDrs2, IDEXrs1, IDEXrs2, EXMEMrd, MEMWBrd; // Access regis
 
 wire [6:0] IFIDop, IDEXop, EXMEMop, MEMWBop; // Access opcodes
 
+reg [31:0] teste, teste2;
+
 always @(posedge clk ) begin // IF/ID
-    Zero_EXMEMB    <= zero;
+    Zero_EXMEMB <= zero;
+    teste <= IMMEDIATE_REG + IDEXPC;
     if(reset == 1'b1) begin
         PC <= BOOT_ADDRESS;
         IFIDIR <= NOP;
     end else begin
-        if((instruction_response == 1'b0 && memory_stall == 1'b0 ) 
-            || flush == 1'b1) begin //instruction_response == 1'b0
+        if((instruction_response == 1'b0 && memory_stall == 1'b0 )) begin //instruction_response == 1'b0
             IFIDIR <= NOP;
         end else begin
             if (memory_stall == 1'b0 && execute_stall == 1'b0) begin
                 if(takebranch == 1'b1) begin
+                    teste2         <= BRANCH_ADDRESS;
                     IFIDIR         <= NOP;
-                    PC             <= IMMEDIATE_REG + IDEXPC; // imediato
+                    PC             <= BRANCH_ADDRESS; // imediato
                     IFIDPC         <= BOOT_ADDRESS;
                 end else begin
                     IFIDIR         <= instruction_data;
@@ -127,8 +130,14 @@ always @(posedge clk ) begin // EX/MEM
     memory_read  <= 1'b0;
     flush        <= 1'b0;
 
-    if(reset == 1'b1) begin
-        EXMEMIR <= NOP; 
+    BRANCH_ADDRESS <= IDEXPC + IMMEDIATE_REG;
+
+    if(IFIDPC != (IDEXPC + IMMEDIATE_REG) && takebranch == 1'b1) begin
+        flush <= 1'b1;
+    end
+
+    if(reset == 1'b1 || flush == 1'b1) begin
+        EXMEMIR <= NOP;
     end else begin
         if(execute_stall == 1'b0 && memory_stall == 1'b0)
             IMMEDIATE_REG <= immediate;