Pull Request Review: X-HEEP on ZCU104

[simone-machetti]

I implemented the following changes:

• Fixed GPIO vendorization to avoid the usage of clock-gating cells.
• Removed constraints file because unused.
• Updated FPGA top-level wrapper to better differentiate between the 3 supported boards (Pynq-Z2, Nexys, and ZCU104) using defines.
• Added software target for ZCU104 to set system clock frequency (15 MHz) and UART baud rate (9600).
• Fixed clock wizard generation script to use the differential 300 MHz input clock.
• Fixed pin assignment to 1) use the differential 300 MHz input clock; 2) remove comments due to wrong syntax (comments must start with ;#); 3) Rearrange some pins for clearness.

This PR can be merged but does NOT completely fix PR esl-epfl#435. Some additional changes have to be implemented:

• Fix hold violations in I2S peripheral when implemented on ZCU104.
• Align and check the correct behavior of Pynq-Z2 and Nexys implementations.