Merge remote-tracking branch 'origin/ls_v2022.04' into lf_v2022.04

* origin/ls_v2022.04: (16 commits)
  armv8: layerscape: fix the function mismatch issue
  net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node
  board: fsl: lx2160aqds: include the lx2160a.h header
  board: fsl: lx2160aqds: add support for SERDES SolidRun#1 protocol 14
  board: fsl: lx2160aqds: add support for SERDES SolidRun#1 protocol 13
  ...

arch/arm/cpu/armv8/fsl-layerscape/lowlevel.S

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * (C) Copyright 2014-2015 Freescale Semiconductor
- * Copyright 2019 NXP
+ * Copyright 2019-2022 NXP
  *
  * Extracted from armv8/start.S
  */
@@ -353,7 +353,7 @@ ENTRY(fsl_ocram_clear_ecc_err)
 	ldr	x0, =DCSR_DCFG_MBEESR2
 	str	w1, [x0]
 	ret
-ENDPROC(fsl_ocram_init)
+ENDPROC(fsl_ocram_clear_ecc_err)
 #endif
 
 #ifdef CONFIG_FSL_LSCH3

arch/arm/dts/Makefile

@@ -464,6 +464,8 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-lx2160a-qds-19-11-x.dtb \
 	fsl-lx2160a-qds-20-x-x.dtb \
 	fsl-lx2160a-qds-20-11-x.dtb \
+	fsl-lx2160a-qds-13-x-x.dtb \
+	fsl-lx2160a-qds-14-x-x.dtb \
 	fsl-lx2162a-qds.dtb\
 	fsl-lx2162a-qds-17-x.dtb\
 	fsl-lx2162a-qds-18-x.dtb\

arch/arm/dts/fsl-lx2160a-qds-13-x-x.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 13.x.x
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-13.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 13.x.x)";
+	compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};

arch/arm/dts/fsl-lx2160a-qds-14-x-x.dts

@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 14.x.x
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-14.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 14.x.x)";
+	compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};

arch/arm/dts/fsl-lx2160a-qds-sd1-13.dtsi

@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 13
+ *
+ * Some assumptions are made:
+ *    * mezzanine card M8 (100G) #1 is connected to IO SLOT 1 - DPMAC 1
+ *    * mezzanine card M8 (100G) #2 is connected to IO SLOT 2 - DPMAC 2
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&inphi1_phy0 &inphi1_phy1>;
+	phy-connection-type = "caui4";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&inphi2_phy0 &inphi2_phy1>;
+	phy-connection-type = "caui4";
+};
+
+&emdio1_slot1 {
+	inphi1_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi1_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};
+
+&emdio1_slot2 {
+	inphi2_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi2_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};

arch/arm/dts/fsl-lx2160a-qds-sd1-14.dtsi

@@ -0,0 +1,30 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 14
+ *
+ * Some assumptions are made:
+ *    * mezzanine card M8 (100G) is connected to IO SLOT 1 - DPMAC 1
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&inphi1_phy0 &inphi1_phy1>;
+	phy-connection-type = "caui4";
+};
+
+&emdio1_slot1 {
+	inphi1_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi1_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};

arch/arm/dts/fsl-lx2160a-rdb.dts

@@ -5,7 +5,7 @@
  * Author:	Priyanka Jain <priyanka.jain@nxp.com>
  *		Sriram Dash <sriram.dash@nxp.com>
  *
- * Copyright 2018 NXP
+ * Copyright 2018-2022 NXP
  *
  */
 
@@ -21,6 +21,12 @@
 	};
 };
 
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&cortina_phy>;
+	phy-connection-type = "xlaui4";
+};
+
 &dpmac3 {
 	status = "okay";
 	phy-handle = <&aquantia_phy1>;
@@ -33,6 +39,18 @@
 	phy-connection-type = "usxgmii";
 };
 
+&dpmac5 {
+	status = "okay";
+	phy-handle = <&inphi_phy>;
+	phy-connection-type = "25g-aui";
+};
+
+&dpmac6 {
+	status = "okay";
+	phy-handle = <&inphi_phy>;
+	phy-connection-type = "25g-aui";
+};
+
 &dpmac17 {
 	status = "okay";
 	phy-handle = <&rgmii_phy1>;
@@ -47,6 +65,11 @@
 
 &emdio1 {
 	status = "okay";
+
+	cortina_phy: ethernet-phy@0 {
+		reg = <0x0>;
+	};
+
 	rgmii_phy1: ethernet-phy@1 {
 		/* AR8035 PHY - "compatible" property not strictly needed */
 		compatible = "ethernet-phy-id004d.d072";
@@ -73,6 +96,14 @@
 	};
 };
 
+&emdio2 {
+	status = "okay";
+	inphi_phy: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+};
+
 &esdhc0 {
 	status = "okay";
 };

board/freescale/common/Makefile

@@ -78,6 +78,7 @@ endif
 obj-$(CONFIG_LS102XA_STREAM_ID)	+= ls102xa_stream_id.o
 
 obj-$(CONFIG_EMC2305)              += emc2305.o
+obj-$(CONFIG_QSFP_EEPROM)	+= qsfp_eeprom.o
 
 # deal with common files for P-series corenet based devices
 obj-$(CONFIG_TARGET_P2041RDB)	+= p_corenet/

board/freescale/common/i2c_mux.c

@@ -1,7 +1,7 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-21 NXP
+ * Copyright 2020-2022 NXP
  * Copyright 2021 Microsoft Corporation
  */
 
@@ -37,4 +37,25 @@ int select_i2c_ch_pca9547(u8 ch, int bus)
 	return 0;
 }
 
+int select_i2c_ch_pca9547_sec(u8 ch, int bus)
+{
+	int ret;
+	DEVICE_HANDLE_T dev;
+
+	/* Open device handle */
+	ret = fsl_i2c_get_device(I2C_MUX_PCA_ADDR_SEC, bus, &dev);
+	if (ret) {
+		printf("PCA: No PCA9547 device found\n");
+		return ret;
+	}
+
+	ret = I2C_WRITE(dev, 0, &ch, sizeof(ch));
+	if (ret) {
+		printf("PCA: Unable to select channel %d (%d)\n", (int)ch, ret);
+		return ret;
+	}
+
+	return 0;
+}
+
 #endif

board/freescale/common/i2c_mux.h

@@ -1,7 +1,7 @@
 /* SPDX-License-Identifier: GPL-2.0+ */
 /*
  * Copyright 2014 Freescale Semiconductor, Inc.
- * Copyright 2020-21 NXP
+ * Copyright 2020-2022 NXP
  * Copyright 2021 Microsoft Corporation
  */
 
@@ -10,6 +10,7 @@
 
 #ifdef CONFIG_FSL_USE_PCA9547_MUX
 int select_i2c_ch_pca9547(u8 ch, int bus);
+int select_i2c_ch_pca9547_sec(u8 ch, int bus);
 #endif
 
 #endif

board/freescale/common/qsfp_eeprom.c

@@ -0,0 +1,90 @@
+// SPDX-License-Identifier: GPL-2.0+
+/*
+ * Copyright 2019-2022 NXP
+ */
+#include <common.h>
+#include <command.h>
+#include <i2c.h>
+#include <linux/ctype.h>
+
+#define DEV_ID_QSFP		0x0c
+#define DEV_ID_QSFP_PLUS	0x0d
+
+static struct __attribute__ ((__packed__)) qsfp_eeprom_map {
+	struct __attribute__ ((__packed__)) qsfp_low_mem {
+	/*	field			byte address */
+	u8	identifier;		/* 0 */
+	u16	status;			/* 1-2 */
+	u8	reserved[124];		/* 3-126 */
+	u8	page_select;		/* 127 */
+	} base;
+
+	struct __attribute__ ((__packed__)) qsfp_page00_mem {
+	/*	field			byte address */
+	u8	identifier;		/* 128 */
+	u8	ext_identifier;		/* 129 */
+	u8	connector;		/* 130 */
+	u8	compat[8];		/* 131-138 */
+	u8	reserved[3];		/* 139-142 */
+	u8	length_fiber[4];
+	u8	length_copper;		/* 146 */
+	u8	tech;			/* 147 */
+	u8	vendor_name[16];	/* 148-163 */
+	u8	reserved2;		/* 164 */
+	u8	oui[3];			/* 165-167 */
+	u8	pn[16];			/* 168-183 */
+	u8	rev[2];			/* 184-185 */
+	u8	reserved3[10];		/* 186-195 */
+	u8	serial[16];		/* 196-211 */
+	u8	date[8];		/* 212-219 */
+	u8	reserved4[35];		/* 220-255 */
+	} page0;
+} qsfp;
+
+unsigned char get_qsfp_compat0(void)
+{
+	int ret;
+	char vendor[20] = {0};
+	char serial[20] = {0};
+	char pname[20] = {0};
+	char mfgdt[20] = {0};
+#ifdef CONFIG_DM_I2C
+	struct udevice *dev;
+#endif
+
+	memset(&qsfp, 0, sizeof(qsfp));
+#ifndef CONFIG_DM_I2C
+	ret = i2c_read(I2C_SFP_EEPROM_ADDR,
+		       0,
+		       I2C_SFP_EEPROM_ADDR_LEN,
+		       (void *)&qsfp,
+		       sizeof(qsfp));
+#else
+	ret = i2c_get_chip_for_busnum(0, I2C_SFP_EEPROM_ADDR, 1, &dev);
+	if (!ret)
+		ret = dm_i2c_read(dev, 0, (void *)&qsfp, sizeof(qsfp));
+#endif
+
+	if (ret != 0) {
+		debug("\nQSFP: no module detected\n");
+		return 0;
+	}
+	/* check if QSFP type */
+	if (qsfp.base.identifier != DEV_ID_QSFP_PLUS) {
+		debug("\nQSFP: unrecognized module\n");
+		return 0;
+	}
+
+	/* copy fields and trim the whitespaces and dump on screen */
+	snprintf(vendor, sizeof(vendor), "%.16s", qsfp.page0.vendor_name);
+	snprintf(serial, sizeof(serial), "%.16s", qsfp.page0.serial);
+	snprintf(pname, sizeof(pname), "%.16s", qsfp.page0.pn);
+	snprintf(mfgdt, sizeof(mfgdt), "%.2s/%.2s/%.2s",
+		 &qsfp.page0.date[0], &qsfp.page0.date[2], &qsfp.page0.date[4]);
+
+	printf("QSFP: detected %s %s s/n: %s mfgdt: %s\n",
+	       strim(vendor), strim(pname), strim(serial), strim(mfgdt));
+
+	/* return ethernet compatibility code*/
+	return qsfp.page0.compat[0];
+}

board/freescale/common/qsfp_eeprom.h

@@ -0,0 +1,14 @@
+/* SPDX-License-Identifier: GPL-2.0+ */
+/*
+ * Copyright 2019-2022 NXP
+ */
+
+#ifndef __QSFP_EEPROM_H_
+#define __QSFP_EEPROM_H_
+/*
+ * QSFP eeprom reader external API interface.
+ */
+
+/* return the ethernet compatibility field 0 */
+unsigned char get_qsfp_compat0(void);
+#endif  /* __QSFP_EEPROM_H_ */

board/freescale/lx2160a/Kconfig

@@ -12,6 +12,15 @@ config SYS_SOC
 config SYS_CONFIG_NAME
 	default "lx2160ardb"
 
+config QSFP_EEPROM
+        bool "Support for reading QSFP+ transceiver eeprom"
+        default y if PHY_CORTINA
+        help
+         This option enables the functionality for reading
+         QSFP+ cable eeprom. It can be used when PHYs are
+         requiring different initialization based on cable
+         type.
+
 source "board/freescale/common/Kconfig"
 endif