mmc: fix boot from eMMC #1

baruchsiach · 2018-02-07T08:07:26Z

When mmc_getcd() returns 1 and init_in_progress is true, the mmc_getcd()
return value is returned to the mmc_start_init() caller, that interprets
it as an error. Just return 0 in this case.

Signed-off-by: Baruch Siach baruch@tkos.co.il

When mmc_getcd() returns 1 and init_in_progress is true, the mmc_getcd() return value is returned to the mmc_start_init() caller, that interprets it as an error. Just return 0 in this case. Signed-off-by: Baruch Siach <baruch@tkos.co.il>

A38x has two DDR clock out signals that are enabled after power on. Those are unrelated to the number of chip selects being used. For instance Naeba board uses single chip select but two DDR components where the first uses clk #0 and the second uses clk #1. Signed-off-by: Rabeeh Khoury <rabeeh@solid-run.com>

i.MX8MQ has two USB3 controllers. Previously we only added the SolidRun#2 controller support in driver. This patch adds the address for SolidRun#1 controller. Signed-off-by: Ye Li <ye.li@nxp.com> Acked-by: Jun Li <jun.li@nxp.com> (cherry picked from commit 3172dab)

Add support for the SERDES SolidRun#1 protocol 13 which enables 2 100G MACs (dpmac.1 and dpmac.2). For this to work, a new DTS file which describes how 2 mezzanine M8 cards can be connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Add support for the SERDES SolidRun#1 protocol 14 which enables a 100G MAC (dpmac.1). For this to work, a new DTS file which describes how the M8 mezzanine card is connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

* origin/ls_v2021.04: (6 commits) net: phy: inphi: change dev_err to pr_err board: freescale: lx2160aqds: include the lx2160a.h header board: lx2160aqds: add support for SERDES SolidRun#1 protocol 14 board: lx2160aqds: add support for SERDES SolidRun#1 protocol 13 net: ldpaa_eth: connect to multiple PHYs/retimers ...

Add support for the SERDES SolidRun#1 protocol 13 which enables 2 100G MACs (dpmac.1 and dpmac.2). For this to work, a new DTS file which describes how 2 mezzanine M8 cards can be connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Add support for the SERDES SolidRun#1 protocol 14 which enables a 100G MAC (dpmac.1). For this to work, a new DTS file which describes how the M8 mezzanine card is connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

* origin/ls_v2022.04: (16 commits) armv8: layerscape: fix the function mismatch issue net: phy: atheros: avoid error in ar803x_of_init() when PHY has no OF node board: fsl: lx2160aqds: include the lx2160a.h header board: fsl: lx2160aqds: add support for SERDES SolidRun#1 protocol 14 board: fsl: lx2160aqds: add support for SERDES SolidRun#1 protocol 13 ...

CID 21694568 (SolidRun#1 of 1): Dereference before null check (REVERSE_INULL) check_after_deref: Null-checking m suggests that it may be null, but it has already been dereferenced on all paths leading to the check. Reported-by: Coverity Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>

CID 22311217 (SolidRun#1 of 1): Operands don't affect result (CONSTANT_EXPRESSION_RESULT) result_independent_of_operands: plat->mpidr == 18446744073709551615UL /* (ulong)-1 */ is always false regardless of the values of its operands. This occurs as the logical operand of if. The mpidr's type is u32, however dev_read_addr returns a value with type fdt_addr_t(phys_addr_t) which is 64bit long. So the check never fail. This patch we still keep mpidr as u32 type, because i.MX8 only has max two cluster, the higher 32bit will always be 0. Use a variable addr to do the check, if check pass, assign the lower 32 bit to plat->mpidr. Reported-by: Coverity Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>

Whenever the CN10K platform was reset from U-Boot, the console driver would initialize a different console (alternating between 0 & 1). This was due to the lack of memory initialization. After a soft-boot on the CN10K, the console driver initialization would see a valid, existing console nexus Signature and would skip initialization. Later, the code would [mis]interpret the existing 'in-use' field and initialize a different console number. If console #0 had previously been in-use, the driver would then initialize console #1. If console #1 had previously been in-use, the driver would then be able to initialize console #0 (alternating between consoles 0 & 1). Fix this problem by checking the 'owner_id' field when an existing console is detected to be 'in-use'. If the existing console is owned by U-Boot, [re]initialize that same console number. Signed-off-by: Rick Farrington <rfarrington@marvell.com> Change-Id: Ib6b9730ac8a35967dd1542670fcb894c29af1418 Reviewed-on: https://sj1git1.cavium.com/c/IP/SW/boot/u-boot/+/92663 Reviewed-by: Aaron Williams <awilliams@marvell.com> Tested-by: Chandrakala Chavva <cchavva@marvell.com>

CID 22311217 (#1 of 1): Operands don't affect result (CONSTANT_EXPRESSION_RESULT) result_independent_of_operands: plat->mpidr == 18446744073709551615UL /* (ulong)-1 */ is always false regardless of the values of its operands. This occurs as the logical operand of if. The mpidr's type is u32, however dev_read_addr returns a value with type fdt_addr_t(phys_addr_t) which is 64bit long. So the check never fail. This patch we still keep mpidr as u32 type, because i.MX8 only has max two cluster, the higher 32bit will always be 0. Use a variable addr to do the check, if check pass, assign the lower 32 bit to plat->mpidr. Reported-by: Coverity Reviewed-by: Ye Li <ye.li@nxp.com> Signed-off-by: Peng Fan <peng.fan@nxp.com>

The driver exists two issues: 1. For RX buffer, current driver release the buffer too early, should wait until free_pkt callback is called. Otherwise, the released buffer will put into rx bd ring again and may be used by enetc when uboot is processing the packet. 2. The RX BD size is only 16 bytes, but cache line is 64 bytes on iMX95, so when flush a free RX BD to submit it ring, the flush may write adjacent BDs which locate in same cache line into memory. It has the possibility that netc has used (filled) this adjacent BD before uboot processes it. So the BD content is overwritten. It will cause polling Ready bit of this BD always failed. We already observed such issue in 1000Mbps network. The patch added the free_pkt call back implementation for issue #1. And for issue #2, it adjusts to submit BDs in cache line size to ring. For example, on iMX95, we submit 4 RX BDs which are in one cache line. The cache operations are also re-fined in the patch with clean codes. Signed-off-by: Ye Li <ye.li@nxp.com> Reviewed-by: Peng Fan <peng.fan@nxp.com> Acked-by: Wei Fang <wei.fang@nxp.com>

Add support for the SERDES #1 protocol 13 which enables 2 100G MACs (dpmac.1 and dpmac.2). For this to work, a new DTS file which describes how 2 mezzanine M8 cards can be connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

Add support for the SERDES #1 protocol 14 which enables a 100G MAC (dpmac.1). For this to work, a new DTS file which describes how the M8 mezzanine card is connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>

mmc: fix boot from eMMC

5c5841f

When mmc_getcd() returns 1 and init_in_progress is true, the mmc_getcd() return value is returned to the mmc_start_init() caller, that interprets it as an error. Just return 0 in this case. Signed-off-by: Baruch Siach <baruch@tkos.co.il>

jnettlet merged commit fd10092 into SolidRun:master-mx6 Feb 7, 2018

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mmc: fix boot from eMMC #1

mmc: fix boot from eMMC #1

baruchsiach commented Feb 7, 2018

mmc: fix boot from eMMC #1

mmc: fix boot from eMMC #1

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baruchsiach commented Feb 7, 2018