board: fsl: lx2160aqds: add support for SERDES SolidRun#1 protocol 13

Add support for the SERDES SolidRun#1 protocol 13 which enables 2 100G MACs (dpmac.1 and dpmac.2). For this to work, a new DTS file which describes how 2 mezzanine M8 cards can be connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
Josua-SR · Apr 14, 2022 · 9af1a17 · 9af1a17
1 parent 3acf328
commit 9af1a17
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Showing 5 changed files with 70 additions and 2 deletions.
diff --git a/arch/arm/dts/Makefile b/arch/arm/dts/Makefile
@@ -464,6 +464,7 @@ dtb-$(CONFIG_FSL_LSCH3) += fsl-ls2080a-qds.dtb \
 	fsl-lx2160a-qds-19-11-x.dtb \
 	fsl-lx2160a-qds-20-x-x.dtb \
 	fsl-lx2160a-qds-20-11-x.dtb \
+	fsl-lx2160a-qds-13-x-x.dtb \
 	fsl-lx2162a-qds.dtb\
 	fsl-lx2162a-qds-17-x.dtb\
 	fsl-lx2162a-qds-18-x.dtb\

diff --git a/arch/arm/dts/fsl-lx2160a-qds-13-x-x.dts b/arch/arm/dts/fsl-lx2160a-qds-13-x-x.dts
@@ -0,0 +1,17 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for SERDES protocol 13.x.x
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+/dts-v1/;
+
+#include "fsl-lx2160a-qds-sd1-13.dtsi"
+
+/ {
+	model = "NXP Layerscape LX2160AQDS Board (DTS 13.x.x)";
+	compatible = "fsl,lx2160aqds", "fsl,lx2160a";
+
+};
diff --git a/arch/arm/dts/fsl-lx2160a-qds-sd1-13.dtsi b/arch/arm/dts/fsl-lx2160a-qds-sd1-13.dtsi
@@ -0,0 +1,49 @@
+// SPDX-License-Identifier: GPL-2.0+ OR X11
+/*
+ * NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 13
+ *
+ * Some assumptions are made:
+ *    * mezzanine card M8 (100G) #1 is connected to IO SLOT 1 - DPMAC 1
+ *    * mezzanine card M8 (100G) #2 is connected to IO SLOT 2 - DPMAC 2
+ *
+ * Copyright 2021-2022 NXP
+ *
+ */
+
+#include "fsl-lx2160a-qds.dtsi"
+
+&dpmac1 {
+	status = "okay";
+	phy-handle = <&inphi1_phy0 &inphi1_phy1>;
+	phy-connection-type = "caui4";
+};
+
+&dpmac2 {
+	status = "okay";
+	phy-handle = <&inphi2_phy0 &inphi2_phy1>;
+	phy-connection-type = "caui4";
+};
+
+&emdio1_slot1 {
+	inphi1_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi1_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};
+
+&emdio1_slot2 {
+	inphi2_phy0: ethernet-phy@0 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x0>;
+	};
+
+	inphi2_phy1: ethernet-phy@1 {
+		compatible = "ethernet-phy-id0210.7440";
+		reg = <0x1>;
+	};
+};
diff --git a/board/freescale/lx2160a/eth_lx2160aqds.c b/board/freescale/lx2160a/eth_lx2160aqds.c
@@ -1,6 +1,6 @@
 // SPDX-License-Identifier: GPL-2.0+
 /*
- * Copyright 2018-2020 NXP
+ * Copyright 2018-2022 NXP
  *
  */
 
@@ -878,6 +878,7 @@ static struct serdes_configuration {
 	/* Serdes block #1 */
 	{1, 3, true},
 	{1, 7, true},
+	{1, 13, true},
 	{1, 19, true},
 	{1, 20, true},
 

diff --git a/configs/lx2160aqds_tfa_defconfig b/configs/lx2160aqds_tfa_defconfig
@@ -48,7 +48,7 @@ CONFIG_CMD_USB=y
 CONFIG_CMD_WDT=y
 CONFIG_CMD_CACHE=y
 CONFIG_OF_CONTROL=y
-CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x  fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x"
+CONFIG_OF_LIST="fsl-lx2160a-qds-3-x-x fsl-lx2160a-qds-7-x-x fsl-lx2160a-qds-19-x-x fsl-lx2160a-qds-20-x-x fsl-lx2160a-qds-3-11-x  fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-7-11-x fsl-lx2160a-qds-19-11-x fsl-lx2160a-qds-20-11-x fsl-lx2160a-qds-13-x-x"
 CONFIG_MULTI_DTB_FIT=y
 CONFIG_ENV_OVERWRITE=y
 CONFIG_ENV_IS_IN_MMC=y