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board: fsl: lx2160aqds: add support for SERDES #1 protocol 14
Add support for the SERDES #1 protocol 14 which enables a 100G MAC (dpmac.1). For this to work, a new DTS file which describes how the M8 mezzanine card is connected on the LX2160AQDS board. Signed-off-by: Ioana Ciornei <ioana.ciornei@nxp.com>
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// SPDX-License-Identifier: GPL-2.0+ OR X11 | ||
/* | ||
* NXP LX2160AQDS device tree source for SERDES protocol 14.x.x | ||
* | ||
* Copyright 2021-2022 NXP | ||
* | ||
*/ | ||
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/dts-v1/; | ||
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#include "fsl-lx2160a-qds-sd1-14.dtsi" | ||
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/ { | ||
model = "NXP Layerscape LX2160AQDS Board (DTS 14.x.x)"; | ||
compatible = "fsl,lx2160aqds", "fsl,lx2160a"; | ||
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}; |
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// SPDX-License-Identifier: GPL-2.0+ OR X11 | ||
/* | ||
* NXP LX2160AQDS device tree source for the SERDES block #1 - protocol 14 | ||
* | ||
* Some assumptions are made: | ||
* * mezzanine card M8 (100G) is connected to IO SLOT 1 - DPMAC 1 | ||
* | ||
* Copyright 2021-2022 NXP | ||
* | ||
*/ | ||
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#include "fsl-lx2160a-qds.dtsi" | ||
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&dpmac1 { | ||
status = "okay"; | ||
phy-handle = <&inphi1_phy0 &inphi1_phy1>; | ||
phy-connection-type = "caui4"; | ||
}; | ||
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&emdio1_slot1 { | ||
inphi1_phy0: ethernet-phy@0 { | ||
compatible = "ethernet-phy-id0210.7440"; | ||
reg = <0x0>; | ||
}; | ||
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inphi1_phy1: ethernet-phy@1 { | ||
compatible = "ethernet-phy-id0210.7440"; | ||
reg = <0x1>; | ||
}; | ||
}; |
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