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@matty0005
Matthew Gilpin matty0005
Tech Ops Engineer

London, United Kingdom

@tmeissner
T. Meissner tmeissner
FPGA-Engineer doing design and verification using VHDL, SystemVerilog, SVA and PSL.

Dresden, Germany

@akaeba
Andreas akaeba
Electronic Designer; Script Engineer; Multilingualist

Chemnitz, Saxony, Germany

@umarcor
Unai Martinez-Corral umarcor

UPV/EHU Bilbo, Bizkaia, Euskadi, Spain, Europe

@rafaelcorsi
Rafael Corsi rafaelcorsi
Professor of Computer Engineering at Insper @Insper

Eng. Computação Insper São Paulo - Brasil

@pcotret
Pascal Cotret pcotret
@ENSTABretagne researcher/lecturer

ENSTA Bretagne Brest, Brittany, France

@hipolitoguzman
Hipólito Guzmán-Miranda hipolitoguzman
Professor at Universidad de Sevilla, Department of Electronic Engineering. Design and verification of digital circuits.

Universidad de Sevilla Sevilla, Spain

@ekb0412
Ekansh Bansal ekb0412
Bachelor of Technology in Electronics and communication from GLA University Mathura. Skilled in Communication, Teamwork, VLSI Design, Cadence

GLA University Mathura

@Marco-Winzker
Marco Winzker Marco-Winzker
Professor for Digital Circuit Design at Bonn-Rhein-Sieg University of Applied Sciences

Hochschule Bonn-Rhein-Sieg St. Augustin, Germany

@mongrelgem
Krishna Subramanian mongrelgem
Aspiring Hardware Engineer
@mriscoc
Miguel Risco-Castillo mriscoc
FPGA system architect with experience in embedded and microcontroller devices. Software, hardware and firmware development.

PULSAR Lima, Peru

@rikka0w0
Rikka0_0小六花 rikka0w0
Power Electronics PhD, STM32, embedded Linux, C, Java, Verilog, Minecraft Modder, Surströmming

UNSW Sydney

@icebreaker-fpga
iCEBreaker icebreaker-fpga
Open Source FPGA development board
@eblot
Emmanuel Blot eblot
Embedded SW developer / ARM - C - Python and other languages

France, Provence

@enjoy-digital
enjoy-digital

EnjoyDigital France

@BrunoLevy
Bruno Levy BrunoLevy
Researcher in computational physics, Scientific director of Inria Quadrant Program, 2018-2022 director of centre Inria Nancy Grand-Est, ERC GOODSHAPE

@inria Saclay, France

@YosysHQ
Yosys Headquarters YosysHQ
Yosys Open SYnthesis Suite
@MegatronJeremy
Vuk Đorđević MegatronJeremy
People's dreams never end

Student of Computer Science Belgrade, Serbia

@zerkman
François Galea zerkman
Software and hardware developer. C, Lua, VHDL, 68000 assembly. Currently developing zeST, a reimplementation of an Atari ST on cheap FPGA prototyping boards.

France

@stnolting
stnolting
Roads? Where we're going we don't need roads. - "Doc" Emmett L. Brown

@Fraunhofer-IMS 🇪🇺 European Union

@howerj
James howerj
Senior Software Engineer

UK

@RickyTino
RickyTino RickyTino
RTL Design / CPU(MIPS, RISC-V) / FPGA

@hitwh-nscscc Beijing, China

@Tabrizian
Iman Tabrizian Tabrizian

NVIDIA Toronto, Canada

@DoctorWkt
Warren DoctorWkt

The Unix Heritage Society

@hamsternz
Mike Field hamsternz

Hamsterworks Chirstchurch, New Zealand

@ultraembedded
ultraembedded
CPU designs, digital HW IP, emulation and embedded system projects

UK

@lilweege
Luigi Quattrociocchi lilweege

@intel Mississauga, ON, Canada

@sam-astro
sam-astro
18-yo developer from the US. Experience with C#, C++, C, Python, backend and frontend with HTML-PHP, Neural Networks, Hardware design, electrical engineering

sam@COMPUTER:~/MIT/$

@MasWag
Masaki Waga MasWag

Kyoto University Kyoto, Japan

@nullpo-head
Takaya Saeki nullpo-head
(☕, 🍣, 🍔) => 💻

Tokyo, Japan (UTC+0900)

@keiichiw
Keiichi Watanabe keiichiw
Software engineer who loves strong type systems

@Google Tokyo