[Backport to 15] Implement SPV_INTEL_tensor_float32_conversion extension (#1656) #1700
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…ion (#1656) This extension adds conversion instruction from float to tensor float (TF32) data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead instruction below uses 32-bit float type to represent TF32 value. Spec: intel/llvm#6990 Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
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Hi, just to let you know, I'm fixing CI issues on all of the release branches, afterwards we can merge all of the backports. |
…de5581c5c00a6b5ef9857655d
MrSidims
approved these changes
Nov 10, 2022
MrSidims
approved these changes
Nov 11, 2022
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This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.
Spec: intel/llvm#6990
Signed-off-by: Sidorov, Dmitry dmitry.sidorov@intel.com