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[SPIR-V][DOC] Add SPV_INTEL_tensor_float32_rounding extension #6990

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@MrSidims MrSidims commented Oct 7, 2022

Signed-off-by: Sidorov, Dmitry dmitry.sidorov@intel.com

@MrSidims MrSidims requested a review from a team as a code owner October 7, 2022 15:17
@MrSidims MrSidims added Documentation Missing documentation for the code, compiler or runtime features, etc. spec extension All issues/PRs related to extensions specifications SPIR-V Issues related to SPIRV-LLVM-Translator labels Oct 12, 2022
MrSidims added a commit to MrSidims/SPIRV-LLVM-Translator that referenced this pull request Oct 17, 2022
@MrSidims
Implement SPV_INTEL_tensor_float32_conversion extension
69ef612 
This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
@MrSidims MrSidims mentioned this pull request Oct 17, 2022
Merged
MrSidims added a commit to MrSidims/SPIRV-LLVM-Translator that referenced this pull request Nov 2, 2022
@MrSidims
Implement SPV_INTEL_tensor_float32_conversion extension
f6ba20a 
This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 4, 2022
@MrSidims
Implement SPV_INTEL_tensor_float32_conversion extension (#1656)
ea3ddc1 
This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
This was referenced Nov 8, 2022
Merged
Merged
Merged
Fznamznon pushed a commit to Fznamznon/llvm that referenced this pull request Nov 8, 2022
@MrSidims @Fznamznon
Implement SPV_INTEL_tensor_float32_conversion extension (intel#1656)
535535b 
This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel#6990

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>

Original commit:
KhronosGroup/SPIRV-LLVM-Translator@ea3ddc1
This was referenced Nov 8, 2022
Merged
Merged
Merged
Merged
Merged
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 11, 2022
@stanleygambarin @MrSidims
[Backport to 8] Implement SPV_INTEL_tensor_float32_conversion extensi…
c371c1b 
…on (#1656) (#1713)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 11, 2022
@stanleygambarin @MrSidims
[Backport to 9] Implement SPV_INTEL_tensor_float32_conversion extensi…
e353ff4 
…on (#1656) (#1712)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 11, 2022
@stanleygambarin @MrSidims
[Backport to 12] Implement SPV_INTEL_tensor_float32_conversion extens…
0a2c704 
…ion (#1656) (#1709)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 11, 2022
@stanleygambarin @MrSidims
[Backport to 15] Implement SPV_INTEL_tensor_float32_conversion extens…
7e583b1 
…ion (#1656) (#1700)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 11, 2022
@stanleygambarin @MrSidims
[Backport to 11] Implement SPV_INTEL_tensor_float32_conversion extens…
97f9259 
…ion (#1656) (#1710)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>

Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 14, 2022
@stanleygambarin @MrSidims
[Backport to 14] Implement SPV_INTEL_tensor_float32_conversion extens…
05c005c 
…ion (#1656) (#1701)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 14, 2022
@stanleygambarin @MrSidims
[Backport to 10] Implement SPV_INTEL_tensor_float32_conversion extens…
3de33db 
…ion (#1656) (#1711)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
MrSidims added a commit to KhronosGroup/SPIRV-LLVM-Translator that referenced this pull request Nov 14, 2022
@stanleygambarin @MrSidims
[Backport to 13] Implement SPV_INTEL_tensor_float32_conversion extens…
eff6d93 
…ion (#1656) (#1702)

This extension adds conversion instruction from float to tensor float (TF32)
data format. TF32 uses 1 bit for a sign, 8 bits for an exponent and 10 bits
for a fraction. This extension doesn’t introduce TF32 type in SPIR-V, instead
instruction below uses 32-bit float type to represent TF32 value.

Spec: intel/llvm#6990

Co-authored-by: Dmitry Sidorov <dmitry.sidorov@intel.com>
@MrSidims MrSidims changed the title [SPIR-V][DOC] Add SPV_INTEL_tensor_float32_conversion extension [SPIR-V][DOC] Add SPV_INTEL_tensor_float32_rounding extension Apr 3, 2023
MrSidims added 2 commits April 3, 2023 07:33
@MrSidims
[SPIR-V][DOC] Add SPV_INTEL_tensor_float32_conversion extension
a85fd0e 
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
@MrSidims
Update the spec
324663e 
Signed-off-by: Sidorov, Dmitry <dmitry.sidorov@intel.com>
@MrSidims MrSidims force-pushed the private/MrSidims/SPIRVTF32Doc branch from eca803f to 324663e Compare April 3, 2023 14:35
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MrSidims commented Apr 3, 2023

@intel/dpcpp-spirv-doc-reviewers please take a look if it's OK to merge here

@MrSidims MrSidims marked this pull request as draft April 4, 2023 16:56
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github-actions bot commented Sep 16, 2024

This pull request is stale because it has been open 180 days with no activity. Remove stale label or comment or this will be automatically closed in 30 days.

@github-actions github-actions bot added the Stale label Sep 16, 2024
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This pull request was closed because it has been stalled for 30 days with no activity.

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