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SoC设计流程总结,主要包括项目初始化/git仓库管理/验证环境搭建/memory生成替换/FPGA环境构建/ASIC环境构建/signoff环境构建等flow

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KingFrige/SoC-Gulp

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SoC-Gulp

This repository contains SoC build flow, such as git/verif/asic/mem/fpga...

How to Quick verif

Install Verilg-Perl

Install NodeJS & npm

Checkout The Code

$ git clone https://gitee.com/korbenyuan/SoC-Gulp.git SoC-Gulp
$ cd SoC-Gulp

$ npm install

$ source sourceme.csh
$ cd ..

Build The Project

# initial project
$ sulp init:project -p test_demo

$ cd test_demo
$ sulp init:repo

$ cd verif/demo/testcase/test

# set EDA tools

$ sulp run:vsim
$ sulp load:wave

TODO

  • 支持verilator仿真器
  • 支持gtkwave 波形工具
  • 支持iverilog仿真器
  • 支持yosys
  • 支持OpenRoad

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SoC设计流程总结,主要包括项目初始化/git仓库管理/验证环境搭建/memory生成替换/FPGA环境构建/ASIC环境构建/signoff环境构建等flow

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