Fix for several problems in dataset

[HejiaZ2023]

This PR addresses a set of fixes span across the testbenches, reference RTL, and prompts to improve correctness and clarity.

Summary of flaws and proposed fixes:

1. Prob 099: DUT initiation port mismatch (Changed Testbench)
2. Prob 118 & 153: Using blocking assignment in sequencial logic (Changed Reference RTL)
3. Prob 134: Unused input clk port (Changed Prompt + v1 interface + Reference RTL + Testbench)
4. Prob 135: Not the FSM itself but the next-state logic should be implemented (Changed v2 Prompt)

All feedbacks are welcome! We're more than happy to discuss these changes further to ensure they align with the benchmark motivation and standards.