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I defined 2 verilog modules, one for DFF and one for EXAMP, I instantiated the DFF module twice in the EXAMP module, but when I use the "show netlist" option to view the schematic, it shows the schematic of the DFF module, while when I change the name of the EXAMP module to A (the initials of the module are sorted before D), the schematic is correct. is it a bug?
netlist show with module name EXAMP(it didnt show correctly)
netlist show with module name A
The text was updated successfully, but these errors were encountered:
I defined 2 verilog modules, one for DFF and one for EXAMP, I instantiated the DFF module twice in the EXAMP module, but when I use the "show netlist" option to view the schematic, it shows the schematic of the DFF module, while when I change the name of the EXAMP module to A (the initials of the module are sorted before D), the schematic is correct. is it a bug?
The text was updated successfully, but these errors were encountered: