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34 Open 51 Closed
34 Open 51 Closed
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Issues list

【0.4.0】运行仿真时提示“非hdl文件”
#88 opened Nov 9, 2024 by Nyarufpga
用MYHDL生成的VCD文件，用插件查看波形时有问题
#86 opened Jun 16, 2024 by xzrsds123
1
未来是否会支持任意形式下全文件夹内的文件都可以解析
#85 opened Apr 27, 2024 by miilTgy
请问是否会加入Vivado TCL自动补全+纠错功能
#83 opened Apr 12, 2024 by yuxuan-z19
how to deal the command not find
#82 opened Jan 16, 2024 by gabiii28
仿真时报错error: Unknown module type
#81 opened Dec 28, 2023 by firerock1
1
使用生成property.json的命令时，报错找不到这个命令
#80 opened Dec 20, 2023 by L-new-H
1
中文README404，仅剩知乎版本
#79 opened Dec 17, 2023 by Liber1917
找不到修改testbench模板的命令
#78 opened Dec 14, 2023 by ycy012
宏 误报错
#77 opened Oct 10, 2023 by filliam9560
I hope to designate the top-level design file within the configuration profile.
#76 opened Sep 26, 2023 by qiQWQwww
10个月没更新，是关闭项目了吗
#75 opened Sep 21, 2023 by wantflyfly
自动例化对于没有写在head的变量不
#73 opened Sep 14, 2023 by JWei0703
使用generate批量例化的模块层级关系在architecture中无法正确地被识别
#72 opened Sep 11, 2023 by Jgfjj
1
Architecture 中无法识别ip文件夹中的ip
#71 opened Sep 8, 2023 by Jgfjj
关于在多个.v文件的补全
#70 opened Sep 6, 2023 by SL8281
verilog module 是否支持数组输入？
#67 opened Aug 28, 2023 by wanghao815
关于Digital的一些建议-望采纳
#66 opened Aug 27, 2023 by 1391074994
1
‘end else if (condition) begin’ style with error
#65 opened Aug 25, 2023 by lydasia
未声明的wire reg 可以随意使用等bug
#64 opened Aug 24, 2023 by 720lhy
1
not a hdlFile
#63 opened Aug 21, 2023 by chansonZ
1
VHDL自动补全的问题
#62 opened Aug 15, 2023 by xqXQzzz1
Linter not working + Extension debug output missing
#59 opened May 11, 2023 by MahmoudKMaarouf
1
Option to ignore scanning certain folders for rtl
#58 opened May 3, 2023 by nitheeshkm
1
"show netlist" option cannot show correctly when other module instantiation in top module bug Something isn't working
#57 opened Apr 8, 2023 by Collect-diamond
2
ProTip! Exclude everything labeled bug with -label:bug.