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Merged
cfernald merged 6 commits into from
Dec 6, 2025
Merged

patina_debugger: Implement single register access #1151

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8682574
patina_debugger: Implement single register access
cfernald Dec 3, 2025
0745d60
disable coverage on debugger internals
cfernald Dec 3, 2025
ba7d6ff
reduce duplicated and explicit sizes
cfernald Dec 5, 2025
e8721ed
naming and slice checks
cfernald Dec 5, 2025
d2e2597
Merge branch 'main' into dbg_single_reg
cfernald Dec 5, 2025
5bede3d
Fix FPSR FPCR mix
cfernald Dec 5, 2025
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14 changes: 14 additions & 0 deletions core/patina_debugger/src/arch.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -96,4 +96,18 @@ pub trait UefiArchRegs: Sized {
fn read_from_context(&mut self, context: &ExceptionContext) {
*self = Self::from_context(context);
}

// Reads a single register from a UEFI context structure.
fn read_register_from_context(
context: &ExceptionContext,
reg_id: <SystemArch as gdbstub::arch::Arch>::RegId,
buf: &mut [u8],
) -> Result<usize, ()>;

// Writes a single register to a UEFI context structure.
fn write_register_to_context(
context: &mut ExceptionContext,
reg_id: <SystemArch as gdbstub::arch::Arch>::RegId,
buf: &[u8],
) -> Result<(), ()>;
}
149 changes: 143 additions & 6 deletions core/patina_debugger/src/arch/aarch64.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -295,8 +295,8 @@ pub struct Aarch64CoreRegs {
pub sp: u64,
/// Instruction pointer
pub pc: u64,
/// Floating point control
pub fpcr: u64,
/// Floating point status
pub fpsr: u64,
/// PE status
pub cpsr: u32,
}
Expand All @@ -323,7 +323,7 @@ impl Registers for Aarch64CoreRegs {

write_bytes!(&self.sp.to_le_bytes());
write_bytes!(&self.pc.to_le_bytes());
write_bytes!(&self.fpcr.to_le_bytes());
write_bytes!(&self.fpsr.to_le_bytes());
write_bytes!(&self.cpsr.to_le_bytes());
}

Expand All @@ -349,7 +349,7 @@ impl Registers for Aarch64CoreRegs {

self.sp = read!(u64);
self.pc = read!(u64);
self.fpcr = read!(u64);
self.fpsr = read!(u64);
self.cpsr = read!(u32);
Ok(())
}
Expand Down Expand Up @@ -393,7 +393,7 @@ impl UefiArchRegs for Aarch64CoreRegs {
],
sp: context.sp,
pc: context.elr,
fpcr: context.fpsr,
fpsr: context.fpsr,
cpsr: context.spsr as u32,
}
}
Expand Down Expand Up @@ -432,9 +432,146 @@ impl UefiArchRegs for Aarch64CoreRegs {
context.lr = self.regs[30];
context.sp = self.sp;
context.elr = self.pc;
context.fpsr = self.fpcr;
context.fpsr = self.fpsr;
context.spsr = self.cpsr as u64;
}

fn read_register_from_context(
context: &ExceptionContext,
reg_id: <super::SystemArch as gdbstub::arch::Arch>::RegId,
buf: &mut [u8],
) -> Result<usize, ()> {
macro_rules! read_field {
($value:expr) => {{
let size = core::mem::size_of_val(&$value);
let bytes = $value.to_le_bytes();
buf.get_mut(0..size).ok_or(())?.copy_from_slice(&bytes);
Ok(bytes.len())
}};
}

match reg_id {
Aarch64CoreRegId::Gpr(n) => match n {
0 => read_field!(context.x0),
1 => read_field!(context.x1),
2 => read_field!(context.x2),
3 => read_field!(context.x3),
4 => read_field!(context.x4),
5 => read_field!(context.x5),
6 => read_field!(context.x6),
7 => read_field!(context.x7),
8 => read_field!(context.x8),
9 => read_field!(context.x9),
10 => read_field!(context.x10),
11 => read_field!(context.x11),
12 => read_field!(context.x12),
13 => read_field!(context.x13),
14 => read_field!(context.x14),
15 => read_field!(context.x15),
16 => read_field!(context.x16),
17 => read_field!(context.x17),
18 => read_field!(context.x18),
19 => read_field!(context.x19),
20 => read_field!(context.x20),
21 => read_field!(context.x21),
22 => read_field!(context.x22),
23 => read_field!(context.x23),
24 => read_field!(context.x24),
25 => read_field!(context.x25),
26 => read_field!(context.x26),
27 => read_field!(context.x27),
28 => read_field!(context.x28),
_ => Err(()),
},
Aarch64CoreRegId::Fp => {
read_field!(context.fp)
}
Aarch64CoreRegId::Lr => {
read_field!(context.lr)
}
Aarch64CoreRegId::Sp => {
read_field!(context.sp)
}
Aarch64CoreRegId::Elr => {
read_field!(context.elr)
}
Aarch64CoreRegId::Fpsr => {
read_field!(context.fpsr)
}
Aarch64CoreRegId::Spsr => {
read_field!(context.spsr as u32)
}
}
}

fn write_register_to_context(
context: &mut ExceptionContext,
reg_id: <super::SystemArch as gdbstub::arch::Arch>::RegId,
buf: &[u8],
) -> Result<(), ()> {
macro_rules! write_field {
($field:expr, $field_type:ty) => {{
let size = core::mem::size_of::<$field_type>();
let value = <$field_type>::from_le_bytes(buf.get(0..size).ok_or(())?.try_into().map_err(|_| ())?);
$field = value;
}};
}

match reg_id {
Aarch64CoreRegId::Gpr(n) => match n {
0 => write_field!(context.x0, u64),
1 => write_field!(context.x1, u64),
2 => write_field!(context.x2, u64),
3 => write_field!(context.x3, u64),
4 => write_field!(context.x4, u64),
5 => write_field!(context.x5, u64),
6 => write_field!(context.x6, u64),
7 => write_field!(context.x7, u64),
8 => write_field!(context.x8, u64),
9 => write_field!(context.x9, u64),
10 => write_field!(context.x10, u64),
11 => write_field!(context.x11, u64),
12 => write_field!(context.x12, u64),
13 => write_field!(context.x13, u64),
14 => write_field!(context.x14, u64),
15 => write_field!(context.x15, u64),
16 => write_field!(context.x16, u64),
17 => write_field!(context.x17, u64),
18 => write_field!(context.x18, u64),
19 => write_field!(context.x19, u64),
20 => write_field!(context.x20, u64),
21 => write_field!(context.x21, u64),
22 => write_field!(context.x22, u64),
23 => write_field!(context.x23, u64),
24 => write_field!(context.x24, u64),
25 => write_field!(context.x25, u64),
26 => write_field!(context.x26, u64),
27 => write_field!(context.x27, u64),
28 => write_field!(context.x28, u64),
_ => return Err(()),
},
Aarch64CoreRegId::Fp => {
write_field!(context.fp, u64);
}
Aarch64CoreRegId::Lr => {
write_field!(context.lr, u64);
}
Aarch64CoreRegId::Sp => {
write_field!(context.sp, u64);
}
Aarch64CoreRegId::Elr => {
write_field!(context.elr, u64);
}
Aarch64CoreRegId::Fpsr => {
write_field!(context.fpsr, u64);
}
Aarch64CoreRegId::Spsr => {
context.spsr = u32::from_le_bytes(buf.try_into().map_err(|_| ())?) as u64;
}
}

Ok(())
}
}

#[derive(Debug)]
Expand Down
137 changes: 134 additions & 3 deletions core/patina_debugger/src/arch/x64.rs
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Original file line number Diff line number Diff line change
Expand Up @@ -256,8 +256,8 @@ pub struct X64CoreRegs {
pub eflags: u64,
/// Segment registers: CS, SS, DS, ES, FS, GS
pub segments: [u32; 6],
/// Control registers: CR0, CR2, CR3, CR4
pub control: [u64; 4],
/// Control registers: CR0, CR2, CR3, CR4, CR8
pub control: [u64; 5],
/// FPU internal registers
pub fpu: [u32; 7],
/// FPU registers: FOP + ST0 through ST7
Expand Down Expand Up @@ -371,7 +371,7 @@ impl UefiArchRegs for X64CoreRegs {
context.fs as u32,
context.gs as u32,
],
control: [context.cr0, context.cr2, context.cr3, context.cr4],
control: [context.cr0, context.cr2, context.cr3, context.cr4, context.cr8],
fpu: [0; 7],
st: [[0; 10]; 9],
}
Expand Down Expand Up @@ -409,6 +409,137 @@ impl UefiArchRegs for X64CoreRegs {
context.cr2 = self.control[1];
context.cr3 = self.control[2];
context.cr4 = self.control[3];
context.cr8 = self.control[4];
}

fn read_register_from_context(
context: &ExceptionContext,
reg_id: <super::SystemArch as gdbstub::arch::Arch>::RegId,
buf: &mut [u8],
) -> Result<usize, ()> {
macro_rules! read_field {
($value:expr) => {{
let size = core::mem::size_of_val(&$value);
let bytes = $value.to_le_bytes();
buf.get_mut(0..size).ok_or(())?.copy_from_slice(&bytes);
Ok(bytes.len())
}};
}

match reg_id {
X64CoreRegId::Gpr(index) => match index {
0 => read_field!(context.rax),
1 => read_field!(context.rbx),
2 => read_field!(context.rcx),
3 => read_field!(context.rdx),
4 => read_field!(context.rsi),
5 => read_field!(context.rdi),
6 => read_field!(context.rbp),
7 => read_field!(context.rsp),
8 => read_field!(context.r8),
9 => read_field!(context.r9),
10 => read_field!(context.r10),
11 => read_field!(context.r11),
12 => read_field!(context.r12),
13 => read_field!(context.r13),
14 => read_field!(context.r14),
15 => read_field!(context.r15),
_ => Err(()),
},
X64CoreRegId::Rip => {
read_field!(context.rip)
}
X64CoreRegId::Eflags => {
read_field!(context.rflags)
}
X64CoreRegId::Segment(index) => match index {
0 => read_field!(context.cs as u32),
1 => read_field!(context.ss as u32),
2 => read_field!(context.ds as u32),
3 => read_field!(context.es as u32),
4 => read_field!(context.fs as u32),
5 => read_field!(context.gs as u32),
_ => Err(()),
},
X64CoreRegId::Control(index) => match index {
0 => read_field!(context.cr0),
1 => read_field!(context.cr2),
2 => read_field!(context.cr3),
3 => read_field!(context.cr4),
4 => read_field!(context.cr8),
_ => Err(()),
},
X64CoreRegId::Fpu(_) => {
buf[..4].fill(0);
Ok(4)
}
X64CoreRegId::St(_) => {
buf[..10].fill(0);
Ok(10)
}
}
}

fn write_register_to_context(
context: &mut ExceptionContext,
reg_id: <super::SystemArch as gdbstub::arch::Arch>::RegId,
buf: &[u8],
) -> Result<(), ()> {
macro_rules! write_field {
($field:expr, $field_type:ty) => {{
let size = core::mem::size_of::<$field_type>();
let value = <$field_type>::from_le_bytes(buf.get(0..size).ok_or(())?.try_into().map_err(|_| ())?);
$field = value.into();
}};
}

match reg_id {
X64CoreRegId::Gpr(index) => {
match index {
0 => write_field!(context.rax, u64),
1 => write_field!(context.rbx, u64),
2 => write_field!(context.rcx, u64),
3 => write_field!(context.rdx, u64),
4 => write_field!(context.rsi, u64),
5 => write_field!(context.rdi, u64),
6 => write_field!(context.rbp, u64),
7 => write_field!(context.rsp, u64),
8 => write_field!(context.r8, u64),
9 => write_field!(context.r9, u64),
10 => write_field!(context.r10, u64),
11 => write_field!(context.r11, u64),
12 => write_field!(context.r12, u64),
13 => write_field!(context.r13, u64),
14 => write_field!(context.r14, u64),
15 => write_field!(context.r15, u64),
_ => return Err(()),
};
}
X64CoreRegId::Rip => context.rip = u64::from_le_bytes(buf.try_into().map_err(|_| ())?),
X64CoreRegId::Eflags => context.rflags = u64::from_le_bytes(buf.try_into().map_err(|_| ())?),
X64CoreRegId::Segment(index) => match index {
0 => write_field!(context.cs, u32),
1 => write_field!(context.ss, u32),
2 => write_field!(context.ds, u32),
3 => write_field!(context.es, u32),
4 => write_field!(context.fs, u32),
5 => write_field!(context.gs, u32),
_ => return Err(()),
},
X64CoreRegId::Control(index) => match index {
0 => write_field!(context.cr0, u64),
1 => write_field!(context.cr2, u64),
2 => write_field!(context.cr3, u64),
3 => write_field!(context.cr4, u64),
4 => write_field!(context.cr8, u64),
_ => return Err(()),
},
X64CoreRegId::Fpu(_) | X64CoreRegId::St(_) => {
// Do nothing.
}
}

Ok(())
}
}

Expand Down
2 changes: 1 addition & 1 deletion core/patina_debugger/src/arch/xml/aarch64_registers.xml
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Original file line number Diff line number Diff line change
Expand Up @@ -34,6 +34,6 @@
<reg name="x30" bitsize="64" type="int64" regnum="30" />
<reg name="sp" bitsize="64" type="data_ptr" regnum="31" />
<reg name="pc" bitsize="64" type="code_ptr" regnum="32" />
<reg name="fpcr" bitsize="64" type="int64" regnum="33" />
<reg name="fpsr" bitsize="64" type="int64" regnum="33" />
<reg name="cpsr" bitsize="32" type="int32" regnum="34" />
</feature>
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